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RTL8181 Wireless LAN Access Point/Gateway Controller
DATA SHEET
ISSUE 4: June 10, 2003
RTL8181
Revision History
Issue No Issue 1 Issue 2 Issue 3 Revision 0.1 0.2 0.3 Details of Change Originator David Hsu Issue Date 11/29/2002 12/9/2002 03/03/2003
Issue 4
1.0
First Release 1. Add a section about system configuration. David Hsu 2. Add some descriptions about register usages. 3. 1. Add Pin number Victor Hsu 2. Add System config register 1. Add a memory map. 2. Modify some register definitions and function descriptions. Victor/David 3. Add package information. 4. Remove 32 bits flash interface support 5. Add pin definitions for Maxim RF interface
2003/06/10
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Table of Contents
1. OVERVIEW................................................................................................................................... 4 2. PIN DESCRIPTION ................................................................................................................. 5 3. ADDRESS MAPPING ........................................................................................................... 12 4. REGISTER MAPPING......................................................................................................... 13 5. SYSTEM CONFIGURATION.......................................................................................... 16 6. INTERRUPT CONTROLLER ........................................................................................ 17 7. MEMORY CONTROLLER............................................................................................... 18 8. ETHERNET CONTROLLER .......................................................................................... 21 9. UART CONTROLLER......................................................................................................... 30 10. TIMER & WATCHDOG ................................................................................................... 33 11. GPIO CONTROL................................................................................................................... 35 12. 802.11B WLAN CONTROLLER ................................................................................. 37 13. PACKAGE INFORMATION ......................................................................................... 48
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1. Overview
RTL8181 is a highly integrated SoC, embedded with a high-performance 32-bit RISC microcontroller, Ethernet and WLAN controller. It is a cost-effective and high- performance solution for the system of wireless LAN Access Point, wireless SOHO router, wireless Internet gateway, etc. System block diagram: EJTAG Timer Watchdog UART GPIO Cache buffer MMU Memory controller Ethernet MAC1
MII
Microprocessor
802.11b MAC/BB
MII
RF transceiver
Ethernet MAC0
Ethernet PHY
LAN
Ethernet PHY
WAN
PCI Bridge PCI device PCI device
Flash
SDRAM
The embedded processor of RTL8181 is Lexra LX5280 32bit RISC CPU, with 8K separate instruction and data caches. A protection unit (MMU) allows the memory be segmented and protected, and this unit is required in the modern operation system (e.g., Linux). The processor pipeline is a dual- issues and 6 stage architecture. The dual- issue CPU fetches two instructions per cycle, and which could allow two instructions are executed concurrently in two pipes via some instructions. Thus, its performance will achieve up to 30% improvement over uni-scalar architecture. Besides, it includes two fast Ethernet MACs, one could be used for LAN interface and the other one could connect to WAN port. An IEEE 802.11b WLAN MAC+Baseband processor is embedded as well. By this build- in wireless controller, it could save a lot of costs and space comparing with the system designed with an external 802.11b adapter. The RTL8181 also integrates with memory controller, which allows customers use external SDRAM and Flash memory in glueless. A PCI interface is supported as well, which enables customers to plug in a PCI device seamlessly. For example, an IEEE 802.11a device could be connected through this PCI interface to provide the WLAN dual mode service.
Features
Core Processor
? ? ? ? ? LX5280 32-bit RISC architecture. Superscalar architecture, containing 2 execution pipelines with better performance Embedded with 8K I-Cache, 8K D-Cache and 4K D-RAM. MMU supported Up to 200MHZ operating frequency
WLAN Controller
? ? ? ? ? Integrated IEEE 802.11b complied MAC and DSSS Baseband processor Support Tx data rate in 11M, 5.5M, 2M and 1M Support long and short preamble Support antenna diversity and AGC. Embedded with encryption/decryption engine for 64 bits and 1 28 bits WEP
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Fast Ethernet Controller
? ? ? ? ? ? Fully compliant with IEEE 802.3/802.3u Support MII interface with full and half duplex capability Support descriptor-based buffer management with scatter-gather capability Support IP, TCP and UDP checksum offload Support IEEE 802.1Q VLAN tagging and 802.1P priority queue. Support full duplex flow control (IEEE 802.3X)
UART
? ? ? 16550 compatible 16 bytes FIFO size Auto CTS/RTS flow control
Memory Controller
? ? ? ? ? Support external 16/32-bit SDRAM with 2 banks access, up to 32M bytes Support external 16-bit Flash memory, up to 16M bytes
PCI Bridge
Support two external PCI devices, complied with PCI 2.2 Support PCI master/slave mode 3.3 and 5V I/O tolerance
GPIO
? ? 16 programmable I/O ports and more 16 port when memory interface is 16 bit mode. Individually configurable to input, output and edge transition
Watchdog/Timer/Counter
? ? A hardware watchdog timer, used to reset processor when system hangs up 4 sets of general timers/counters
EJTAG
? Standard P1149.1 JTAG interface for testing and debugging
2. Pin Description
Typ Pin No(208) Pin No(292) Description e Memory Interface MD[31-0] I/O 198,197,195 P1,P2,N3,N Data for SDRAM, Flash. ,194,193,19 2,N1,M3,M 2,191,190,1 2,M1,L2,L3, 88,187,185, L1,K2,K3,K 184,182,181 1,J2,J1,H2, ,180,179,17 H1,G2,F1,G 7,176,174,1 3,F2,E1,F3, 73,171,170, E2,D1,D2,E 169,168,166 3,A1,B1,B2, ,165,163,16 C3 2,161,160,1 59,158 MA[21-0]/ O 115,116,118 B14,A15,D1 Address for SDRAM, Flash. DQM[3-0] ,119,121,12 4,C14,A14, MA[15-18] mapping to DQM[3-0] for SDRAM 2,124,125,1 C13,B13,C1 27,128,130, 2,A12,C11, 131,133,134 B11,C10,A1 ,135,136,13 1,B10,A10, 5 Symbol
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8,139,141,1 42,144 152 150 149 157 156 154 153 147 146 16 14 15 17 208,178,164 ,151,137,12 3,83,58,52,3 0,4 C9,A9,B9,A 7,C7,B7,A6 A5 C5 B5, D4 A2 B4 A4 D5 B6 Y8 W7 Y7 V8
K4,G4,F4,E I/O power 3.3V (Digital), 4,D13,D12, D11,B18,B1 7,A19,A18, K17,P4,P17, R17,U7,U8, U14,U15 GP[11-1] P 204,189,167 K12,K11,K I/O 3.3V GND (Digital) ,155,140,12 10,K9,K8,J1 6,80,63,42,2 2,J11,J10,J9 0,1 ,H11,H10,K 13,L8,L9,L1 0,L11,L12,L 13,M9,M10, M11,N10,N 11 PD[7:5],PS P 183,175,132 N17,M4,L4, Core logic power 1.8V (Digital) [5:3] ,196,148,74 N4,U10,U1 1 GD[7-5],G P 186,172,129 M8,J13,J8,R Core logic 1.8Ground (Digital) S[5-3] ,199,145,77 4,R3,J17 PA[6-1] P 111,104,92,1 D16,D15,C1 Wireless LAN power 3.3V(Analog) 13,98,89 5,C17,D20, G19 GA[6-1],G P 108,107,95, G17,F17,E1 Wireless LAN Ground (Analog), GA7 VSUB A7 114,100,86, 7,C16,D19, 112 G20,A20 PD[4-1] P 120,72,48,2 J4,H4,D10, Core logic 1.8V power(Digital) 8 D9 GD[4-1] P 117,69,45,2 H13,H12,H Core logic LAN Ground(Digital) 5 9,H8,M12, M13,N8,N9, N12,N13 PS[2:1] P 36,7 D6,C6,U4,U Core logic power 1.8V(Digital) 5,U12,L17, M17 GS[2:1] P 39,10 D8,D7,T4,U Core logic 1.8V GND 6,U13 WLAN Traffic LED Control WLTXRX O 65 T19 WLAN Tx/Rx traffic indicator or JTAG reset. LED0B 6
M_CLK O MCS0B O MCS1B O RASB/OE O B CASB O MWENB O MCKE O MCS2B O MCS3B O UART Interface URTSB O I UCTSB USIN I USOUT O Power & GND PP[11-1] P
SDRAM clock Bank 0 chip select FLASH chip select Bank 1 chip select FLASH chip select Raw address strobe for SDRAM; Output enable for Flash Column address strobe Write enable for SDRAM and Flash SDRAM Clock enable Bank 0 chip select for SDRAM Bank 1 chip select for SDRAM UART Request to send UART Clear to send. UART data receive serial input UART data transmit serial output
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WLTXRX O 64 LED1B RF Interface for Intersil RIFSCK O 66 RIFSD O 67 RFLE O 68 IFLE/AGC O 70 SET 71 CALEN/ O AGCRESE T LNA_HL O ANTSELP O 73 75 T18 WLAN Tx/Rx traffic indicator or JTAG CLK
R20 P19 P18 N18 P20
M19 M20
ANTSELN O
76
L18
TRSWP TRSWN VCOPDN/ PHITXI PAPE PE1/PHIT XQ
O O O O O
78 79 81 82 84
L19 L20 K20 K19 K18
3-wire Bus Clock 3-wire Bus Data 3-wire Bus Enable IF_LE of the Intersil Chipset: PLL Synthesizer Serial Interface Latch Enable Control. CMOS output. CAL_EN of the Intersil Chipset: CMOS output for activation of DC offset adjust circuit. A rising edge activates the calibration cycle, which completes within a programmable time and holds the calibration while this pin is held high. In applications where the synthesizer is not used, this pin needs to be grounded. Drive to the RF AGC Stage Attenuator: CMOS digital. Antenna Select +: The antenna selects signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSELN for differential drive of ant enna switches. Antenna Select -: The antenna selects signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSELP for differential drive of antenna switches. Transmit/Receive Control Output Pin as VCO VCC Power Enable/Disable. Transmit PA Power Enable The combination of PE1 and PE2 are as follows: 00: Power Down State, PLL Registers in Save Mode, Inactive PLL, Active Serial 11: Receive State, Active PLL 10: Transmit State, Active PLL 01: Inactive Transmit and Receive States, Active PLL, Active Serial Interface Output Pin as PE2: Refer to PE1 description. Receive (Rx) In-phase Differential Analog Data Receive (Rx) Quadrature Differential Analog Data Analog Input to the Receive Power A/D Converter for AGC Control Input to the Transmit Power A/D Converter for Transmit AGC Control Voltage Reference for ADC and DAC Transmit (TX) In-phase Differential Analog Data Trans mit (TX) Quadrature Differential Analog Data Analog Drive to the Transmit IF Power Control Analog Drive to the Receive IF AGC Control 3-wire Bus Clock: The serial clock output, with resistive dividers on board to allow programming from +5V levels. 3-wire Bus Data: Serial data output, with resistive dividers on board to allow programming from +5V levels. 3-wire Bus Enable: Enable serial port output, with resistive dividers on board to allow programming from +5V levels. Not used in the RFMD RF chipset. Not used in the RFMD RF chipset. RF2494 Gain Select: Digital output.
PE2 O 85 RXIP AI 110 RXIN AI 109 RXQP AI 106 RXQN AI RSSI AI 105 TXDET AI 102 VREFI AI 101 TXIP AO 97 TXIN AO 96 TXQP AO 94 TXQN AO 93 TXAGC AO 91 RXAGC AO 90 RF Interface for RFMD RIFSCK O 66 RIFSD RFLE O O 67 68 70 71 73
J20 B19 B20 C18,C19 D17 D18 C20 E19,F18 E20,F20 F19 G18 R20 P19 P18 N18 P20 M19
IFLE/AGC X* SET CALEN/ X AGCRESE T LNA_HL O
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ANTSELP O 75 M20 Antenna Select +: The antenna selects signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSEL- for differential drive of antenna switches. Not used in the RFMD RF chipset. Not used in the RFMD RF chipset. Not used in the RFMD RF chipset. Output Pin as VCO VCC Power Enable/Disable. Power Control Output for RF2189 PA: 0V to +3.3V. This pin is the shutdown control output on board regulator when the RF Module enters either power-saving or standby mode. Output pin as RF2948 RX EN/ TX EN, RF2494 OE and CE: Refer to the RF2948 and RF2494 datasheets. Receive (Rx) In-phase Analog Data in Single Ended Not used in RFMD RF chipset. Receive (Rx) Quadrature-phase Analog Data in Single Ended Not used in RFMD RF chipset. Not used in RFMD RF chipset. To internal ADC which detects transmit power. Reference voltage for ADC, DAC from VREF1 of RF2948B. Transmit (TX) In-phase Digital Data: Combining before connecting to TX_I of RF2948B. Transmit (TX) Quadrature Digital Data: Combining before connecting to TX_Q of RF2948B. Transmit gain control output to RF2948. RF2948 VGC receiver gain control analog output. 3-wire Bus Clock: The pin RIFSCK is the "shift clock" output. If the 3-wire bus is enabled, address or data bits will be clocked out from the RIFSD pin with rising edges of RIFSCK. 3-wire Bus Data: The pin RIFSD is the output "data" pin. The detail timing is on 11.3.3. 3-wire Bus Enable: The pin RFLE is an "enable" signal. It is level sensitive: If RFLE is of LOW value, the 3-wire bus interface on the SA2400 is enabled. This means that each rising edge on the RIFSCK pin will be taken as a shift cycle, and address/data bits are expected on RIFSD. If RFLE is HIGH, the 3-wire bus interface is disabled. No register settings will change regardless activity on RIFSCK and RIFSD. AGCSET of the Philips Chipset: On the digital output pin AGCRESET, a 0 => 1 transition clears AGCSET of SA2400 to logic 0 and SA2400 starts the AGC cycle. At end of AGC cycle, the AGCSET of SA2400 is asserted to logic 1. Then, AGCRESET will return to logic low. AGCRESET of the Philips Chipset: Please refer to the AGCSET description and Philips SA2400 datasheet. Not used in Philips RF chipset. Antenna Select +: The antenna selects signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSEL- for differential drive of antenna switches. Antenna Select -: The antenna selects signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSEL+ for differential drive of antenna switches. Transmit and Receive Switch Control: This is a complement for TRSW-. 1:TX 0:RX 8
ANTSELN TRSWP TRSWN VCOPDN/ PHITXI PAPE PE1/PHIT XQ PE2
X X X O/I O O O
76 78 79 81 82 84 85
L18 L19 L20 K20 K19 K18 J20 B19 B20 C18 C19 D17 D18 C20 E19 F18 E20 F20 F19 G18 R20
RXIP AI* 110 RXIN X 109 RXQP AI 106 RXQN X 105 RSSI X 103 TXDET AI 102 VREFI AI 101 TXIP AO 97 TXIN AO 96 TXQP AO 94 TXQN AO 93 TXAGC AO 91 RXAGC AO 90 RF Interface for Philip RIFSCK O 66
RIFSD RFLE
O O
67 68
P19 P18
IFLE/AGC I SET
70
N18
CALEN/ O AGCRESE T LNA_HL X* ANTSELP O
71
P20
73 75
M19 M20
ANTSELN O
76
L18
TRSWP
O
78
L19
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TRSWN O 79 L20 K20 Transmit and Receive Switch Control: This is a complement for TRSW+. 1:RX 0:TX Output Pin as Transmit (TX) In-phase Digital Data of the Philips Chipset. This function is valid on Tx digital mode (AnalogPhy = Digital on EEPROM writer program). Transmit PA Power Enable: Assert high when starting transmission. Transmit (TX) Quadrature Digital Data of Philips Chipset. This function is valid on Tx digital mode (AnalogPhy = Digital on EEPROM writer program). Output Pin as TX/RX Control: 1:RX 0:TX Receive (Rx) In-phase Analog Data: Positive path of differential pair. Receive (Rx) In-phase Analog Data: Negative path of differential pair. Receive (Rx) Quadrature-phase Analog Data: Positive path of the differential pair. Receive (Rx) Quadrature-phase Analog Data: Negative path of the differential pair. Received Signal Strength Indication: To internal ADC. Transmit Power Detect: To internal ADC which detects transmit power. Reference Voltage for ADC & DAC Transmit (Tx) In-phase Analog Data: Positive path of differential pair. This function is valid on Tx digital mode (AnalogPhy = Digital on EEPROM writer program). Transmit (Tx) In-phase Analog Data: Negative path of differential pair. This function is valid on Tx digital mode (AnalogPhy = Digital on EEPROM writer program). Transmit (Tx) Quadrature-phase Analog Data: Positive path of the differential pair. This function is valid on Tx digital mode (AnalogPhy = Digital on EEPROM writer program). Transmit (Tx) Quadrature-phase Analog Data: Negative path of the differential pair. This function is valid on Tx digital mode (AnalogPhy = Digital on EEPROM writer program). Not used in Philips RF chipset Not used in Philips RF chipset 3-wire Bus Clock: The serial clock output 3-wire Bus Data: Serial data output 3-wire Bus Enable: Enable serial port output Not used in the Maxim RF chipset. Not used in the Maxim RF chipset.
VCOPDN/ O/I 81 PHITXI/ PAPE O PE1/PHIT O XQ PE2 O 82 84 85
K19 K18 J20
RXIP RXIN RXQP RXQN RSSI TXDET VREFI TXIP
AI* 110 AI 109 AI 106 AI AI AI AI AO 105 103 102 101 97
B19 B20 C18 C19 D17 D18 C20 E19
TXIN
AO 96
F18
TXQP TXQN
AO 94 AO 93
E20 F20
TXAGC X 91 RXAGC X 90 RF Interface for Maxim RIFSCK O 66 RIFSD O 67 RFLE O 68 IFLE/AGC X* 70 SET CALEN/ X 71 AGCRESE T LNA_HL O 73 ANTSELP O 75
F19 G18 R20 P19 P18 N18 P20
M19 M20
ANTSELN X
76
L18
TRSWP X 78 TRSWN X 79 VCOPDN/ O/I 81 PHITXI
L19 L20 K20
LNA Gain Select Logic Output: Logic high for LNA high-gain mode, logic low for LNA low- gain mode. Antenna Select +: The antenna selects signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSEL- for differential drive of antenna switches. Antenna Select -: The antenna selects signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSEL+ for differential drive of antenna switches. Not used in the Maxim RF chipset. Not used in the Maxim RF chipset. Output Pin as VCO VCC Power Enable/Disable.
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PAPE O PE1/PHIT O XQ PE2 O RXIP AI* RXIN X RXQP AI RXQN X RSSI X TXDET AI VREFI AI TXIP AO TXIN AO TXQP AO TXQN AO TXAGC AO RXAGC AO Miscellaneous R10K I/O XO O 82 84 85 110 109 106 105 103 102 101 97 96 94 93 91 90 99 87 K19 K18 J20 B19 B20 C18 C19 D17 D18 C20 E19 F18 E20 F20 F19 G18 E18 H18 H19 A13,B12,A8 ,C8,B8,C4, B3,A3,C2,D 3,C1,G1,H3, J3,V2,V1,V 3,W2,V4,w 3,Y3,W6,Y 6,V7,Y14, W14,Y15,Y 19,U16,R18 ,T20,R19 W20,V19,U 17,V20 Transmit PA Power Enable: Assert high when starting transmission. Not used in the Maxim RF chipset. Not used in the Maxim RF chipset now. Receive (Rx) In-phase Analog Data: Positive path of differential pair. Receive (Rx) In-phase Analog Data: Negative path of differential pair. Receive (Rx) Quadrature-phase Analog Data: Positive path of differential pair. Receive (Rx) Quadrature-phase Analog Data: negative path of differential pair. Not used in Maxim RF chipset. To internal ADC which detects transmit power. Not used in Maxim RF chipset. Transmit (TX) In-phase Digital Data: Combining before connecting to TX_I of RF2948B. Transmit (TX) Quadrature Digital Data: Combining before connecting to TX_Q of RF2948B. Transmit gain control output to RF2948. Analog Drive to the Receive r AGC Control. This pin must be pulled low by a 10K O resistor. Crystal Feedback Output: This output is reserved for crystal connection. It should be left open when XI is driven with an external 44 MHz oscillator. 44 MHz OSC Input PCI address and data multiplexed pins. The address phase is the first clock cycle in which FRAMEB is asserted. During the address phase, AD31-0 contains a physical address (32 bits). For I/O, this is a byte address, and for configuration and memory, it is a double-word address. Write data is stable and valid when IRDYB is asserted. Read data is stable and valid when TRDYB is asserted. Data I is transferred during those clocks where both IRDYB and TRDYB are asserted.
XI I 88 PCI Interface AD31-0 T/S *X
C/BE3-0
T/S *X
CLK
O
*X
N19 P3 N20
DEVSELB S/T/ *X S FRAMEB S/T/ *X S
GNTB REQB IDSEL INTAB IRDYB
T/S *X T/S *X O *X O/D *X S/T/ *X S
H20 J18 A16 A17 M18
PCI bus command and byte enables multiplexed pins. During the address phase of a transaction, C/BE3-0 define the bus command. During the data phase, C/BE3-0 are used as Byte Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. C/BE0 applies to byte 0, and C/BE3 applies to byte 3. PCI clock: This clock input provides timing for all PCI transactions and is input to the PCI device. Device Select: As a bus master, the RTL8181 samples this signal to insure that a PCI target recognizes the destination address for the data transfer. Cycle Frame: As a bus master, this pin indicates the beginning and duration of an access. FRAMEB is asserted low to indicate the start of a bus transaction. While FRAMEB is asserted, data transfer continues. When FRAMEB is deasserted, the transaction is in the final data phase. As a target, the device monitors this signal before decoding the address to check if the current transaction is addressed to it. Grant:Grant indicate to the agent that access to the bus has been granted. Request: Request indicates to the ar biter that this agent desires use of the bus. Initialization Device Select: This pin is used as a chip select during configuration read and write transactions.. Interrupt A: Used to request an interrupt. It is asserted low when an interrupt condition occurs, as defined by the Interrupt Status, Interrupt Mask. Initiator Ready: This indicates the initiating agent's ability to complete the current data phase of the transaction. As a bus master, this signal will be asserted low when the RTL8181 is ready to 10
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complete the current data phase transaction. This signal is used in conjunction with the TRDYB signal. Data transaction takes place at the rising edge of CLK when both IRDYB and TRDYB are asserted low. As a target, this signal indicates that the master has put data on the bus. Target Ready: This indicates the target agent's ability to complete the current phase of the transaction. As a bus master, this signal indicates that the target is ready for the data during write operations and with the data during read operations. As a target, this signal will be asserted low when the (slave) device is ready to complete the current data phase transaction. This signal is used in conjunction with the IRDYB signal. Data transaction takes place at the rising edge of CLK when both IRDYB and TRDYB are asserted low. Parity: This signal indicates even parity across AD31-0 and C/BE3-0 including the PAR pin. PAR is stable and valid one clock after each address phase. For data phase, PAR is stable and valid one clock after either IRDYB is asserted on a write transaction or TRDYB is asserted on a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase. As a bus master, PAR is asserted during address and write data phases. As a target, PAR is asserted during read data phases. Stop: Indicates that the current target is requesting the master to stop the current transaction. Reset: Active low signal to reset the PCI device. TXC is a continuous clock that provides a timing reference for the transfer of TXD[3:0], TXE. In MII mode, it uses the 25 MHz or 2.5 MHz supplied by the external PMD device. Indicates the presence of valid nibble data on TXD[3:0].
TRDYB
S/T/ *X S
J19
PAR
T/S *X
R2
STOPB
S/T/ *X S RSTB O *X MII Interface LTXC, I 53,31 WTXC LTXEN, O WTXEN LTXD[3-0] O , WTXD [3-0] 59,37
B16 B15 Y20 W11 T17
57,56,55,54 V18,V17,W Four parallel transmit data lines which are driven synchronous t o the TXC for 35,34,33,32 19,W18 transmission by the external physical layer chip. V12,Y13,W 12,Y12 LRXC, I 51,29 W17,V11 This is a continuous clock that is recovered from the incoming data. MRXC is WRXC 25MHz in 100Mbps and 2.5Mhz in 10Mbs. LCOL, I 60,38 U18,V13 This signal is asserted high synchronously by the external physical unit upon WCOL detection of a collision on the medium. It will remain asserted as long as the collision condition persists. LRXDV, I 43,44 W16,W9 Data valid is asserted by an external PHY when receive data is present on the WRXDV RXD[3:0] lines, and it is deasserted at the end of the packet. This signal is valid on the rising of the RXC. LRXD[3-0 I 50,49,47,46 V15,V16,Y This is a group of 4 data signals aligned on nibble boundaries which are driven ], 27,26,24,23 18,Y17,Y11 synchronous to the RXC by the external physical unit WRXD[3,W10,V10, 0] Y10 LRXER, I 44,22 V14,V9 This pin is asserted to indicate that invalid symbol has been detected in 100Mbps WRXER MII mode. This signal is synchronized to RXC and can be asserted for a minimum of one receive clock. LMDC, O 40,18 W15,W8 Management Data Clock: This pin provides a clock synchronous to MDIO, WMDC which may be asynchronous to the transmit TXC and receive RXC clocks. LMDIO, I/O 41,19 Y16,Y9 Management Data Input/Output: This pin provides the bi-directional signal used WMDIO to transfer management information. GPIO GPIOB[11- I/O 205,206,207, U1,U2,U3, General purpose I/O pins group B pins 11 to 0. If ICFG[5-4] power on latch 0] 2,3,5,6,8,9,1 W1,Y1,Y2, =[1-0]. GPIO[5-2] mapping to JTAG_TDO(JTAG test data 1,12,13 W4,V5,Y4, output),JTAG_TRSTN(JTAG reset),JTAG_TMS(JTAG test mode W5,V6,Y5 select),JTAG_TDI(JTAG test data input). GPIOB[15 I/O 200,201,202, R1,T1,T2,T General purpose I/O pins group B pin 15 to 12. -12] 203 3
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RTL8181 *A=Analog signal *X=Not used .
3. Address Mapping
The RTL8181 supports up to 4 gigabytes of address space. The memory map of RTL8181 is managed by MMU, which will translate the virtual address to physical address. The memory is segmented into four regions by its access mode and caching capability as shown in following table. Segment Size KUSEG KSEG0 KSEG1 KSEG2 KSEG2 2048M 512M 512M 512M 512M Caching cacheable cacheable uncachable cacheable cacheable Virtual address range 0x0000_0000-0x7fff_ffff 0x8000_0000-0x9fff_ffff 0xa000_0000-0xbfff_ffff 0xc000_0000-0xfeff_ffff 0xff00_0000-0xffff_ffff Physical address range set in TLB 0x0000_0000-0x1fff_ffff 0x0000_0000-0x1fff_ffff set in TLB 0xff00_0000-0xffff_ffff Mode user/kernel kernel kernel kernel kernel
The RTL8181 has two memory mapping modes: direct memory mapping and TLB (Translation Look-aside Buffer) address mapping. When virtual address is located in the regions KSEG0, KSEG1 or higher half of KSEG2 segments, it physical address will be mapped directly from virtual address with an offset. If virtual address used is in the regions of KUSEG or lower half of KSEG2 segment, its physical address will be referred from TLB entry. RTL8181 contains 16 TLB entries, each of which maps to a page, with read/write access, cache-ability and process id. In RTL8181, SDRAM is mapped from physical address 0x0000_0000 to maximum 0x01ff_ffff (32M bytes). After reset, RTL8181 will start to fetch instructions from physical address 0x1fc0_0000, the starting address of flash memory. The flash memory is mapped from physical address 0x1fc0_0000 to maximum 0x1fff_ffff (4M bytes).
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Memory map (without TLB):
Virtual Address Physical Address 0x8000_0000
Cacheable
region
SDRAM (32Mbyte) None cacheable region
0x0000_0000
0x81ff_ffff 0xa000_0000
0x01ff_ffff
0xa1f f_ffff
0xbfc0_0000
None cacheable region
0x1fc0_0000
Flash (4Mbyte)
0x1fff_ffff
0xbfff_ffff
The memory map of RTL8181 I/O devices and registers are located in KSEG1 segment (uncacheable region). The following table illustrates the address map: Virtual address range Size (bytes) Mapped device 0xBD01_0000 - 0xBD01_0FFF 4K Special function registers (note) 0xBD01_1000 - 0xBD01_1FFF 4K Memory controller registers 0xBD20_0000 - 0xBD2F_FFFF 1M Ethernet0 0xBD30_0000 - 0xBD3F_FFFF 1M Ethernet1 0xBD40_0000 - 0xBD4F_FFFF 1M WLAN controller 0xBD50_0000 - 0xBD5F_FFFF 1M IO map address of PCI device 0xBD60_0000 - 0xBD6F_FFFF 1M Memory map address of PCI device 0xBD70_0000 - 0xBD77_FFFF 512K Configuration space of PCI device0 0xBD78_0000 - 0xBD7F_FFFF 512K Configuration space of PCI device1 NOTE: The special function includes interrupt control, timer, watchdog, UART, and GPIO.
4. Register Mapping
The following table displays the address mapping of the all registers: Virtual Address Register Symbol Interrupt Controller 0xBD01_0000 GIMR 0xBD01_0004 GISR GPIO 0xBD01_0040 PABDIR 0xBD01_0044 PABDATA 0xBD01_0048 PBIMR 0xBD01_004C PBISR Timer 0xBD01_0050 TCCNT Register Name Global mask register Global interrupt status register Port A/B direction register Port A/B data register Port B interrupt mask register Port B interrupt register Timer/Counter control register
CONFIDENTIAL
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v1.0
RTL8181
0xBD01_0054 0xBD01_0058 0xBD01_005C 0xBD01_0060 0xBD01_0064 0xBD01_0068 0xBD01_006C 0xBD01_0070 0xBD01_0074 0xBD01_0078 0xBD01_007C UART 0xBD01_00C3 0xBD01_00C3 0xBD01_00C3 0xBD01_00C7 0xBD01_00C7 0xBD01_00CB 0xBD01_00CB 0xBD01_00CF 0xBD01_00D3 0xBD01_00D7 0xBD01_00DB 0xBD01_00DF System Config register 0xBD01_0100 TCIR CBDR WDTCNR TC0DATA TC1DATA TC2DATA TC3DATA TC0CNT TC1CNT TC2CNT TC3CNT UART_RBR UART_THR UART_DLL UART_DLM UART_IER UART_IIR UART_FCR UART_LCR UART_MCR UART_LSR UART_MSR UART_SCR Timer/Counter interrupt register Clock division base register Watchdog timer control register Timer/Counter 0 data register Timer/Counter 1 data register Timer/Counter 2 data register Timer/Counter 3 data register Timer/Counter 0 count register Timer/Counter 1 count register Timer/Counter 2 count register Timer/Counter 3 count register UART receiver buffer register UART transmitter holding register UART divisor latch LSB UART divisor latch MSB UART interrupt enable register UART interrupt identification register UART FIFO control register UART line control register UART modem control register UART line status register UART modem status register UART scratch register
BRIDGE_REG
0xBD01_0104 PLLMN_REG 0xBD01_0108 MEM_REG 0xBD01_0109 CPU_REG Memory controller 0xBD01_1000 MCR 0xBD01_1004 MTCR0 0xBD01_1008 MTCR1 Ethernet0 0xBD20_0000 ETH0_CNR1 0xBD20_0004 ETH0_ID 0xBD20_000C ETH0_MAR 0xBD20_0014 ETH0_TSAD 0xBD20_0018 ETH0_RSAD 0xBD20_0020 ETH0_IMR 0xBD20_0024 ETH0_ISR 0xBD20_0028 ETH0_TMF0 0xBD20_002C ETH0_TMF1 0xBD20_0030 ETH0_TMF2 0xBD20_0034 ETH0_TMF3 0xBD20_0038 ETH0_MII 0xBD20_003C ETH0_CNR2 0xBD20_0040 ETH0_UAR 0xBD20_0080 ETH0_MPC 0xBD20_0083 ETH0_TXCOL 0xBD20_0085 ETH0_RXER Ethernet1 0xBD30_0000 ETH1_CNR1 0xBD30_0004 ETH1_ID 0xBD30_000C ETH1_MAR
WLAN, Eherernet0, Ethernet1 and PCI bridge configuration register DLL M ,N parameter Memory clock setting CPU clock setting Memory configuration register Memory timing configuration register 0 Memory timing configuration register 1 Ethernet0 control register 0 Ethernet0 ID Ethernet0 multicast register Ethernet0 transmit starting address descriptor Ethernet0 receive starting address descriptor Ethernet0 interrupt mask register Ethernet0 interrupt status register Ethernet 0 Type filter0 register Ethernet 0 Type filter1 register Ethernet 0 Type filter2 register Ethernet 0 Type filter3 register Ethernet0 MII access register Ethernet0 control register 2 Ethernet0 unicast address register Ethernet0 mismatch packet counter Ethernet0 transmit collision counter Ethernet0 receive error count Ethernet1 control register 0 Ethernet1 ID Ethernet1 multicast register
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v1.0
RTL8181
0xBD30_0014 0xBD30_0018 0xBD30_0020 0xBD30_0024 0xBD30_0028 0xBD30_002C 0xBD30_0030 0xBD30_0034 0xBD30_0038 0xBD30_003C 0xBD30_0080 0xBD30_0083 0xBD30_0085 WLAN controller 0xBD40_0000 0xBD40_0008 0xBD40_0018 0xBD40_0020 0xBD40_0024 0xBD40_0028 0xBD40_002C 0xBD40_002E 0xBD40_0037 0xBD40_003C 0xBD40_003E 0xBD40_0040 0xBD40_0044 0xBD40_0048 0xBD40_004C 0xBD40_0050 0xBD40_0051 0xBD40_0053 0xBD40_0054 0xBD40_0058 0xBD40_0059 0xBD40_005A 0xBD40_005B 0xBD40_005F 0xBD40_0070 0xBD40_0072 0xBD40_0074 0xBD40_0076 0xBD40_0078 0xBD40_007A 0xBD40_007C 0xBD40_007D 0xBD40_007E 0xBD40_0080 0xBD40_0090 0xBD40_00A0 0xBD40_00B0 0xBD40_00C0 0xBD40_00D8 0xBD40_00D9 0xBD40_00DC 0xBD40_00DE 0xBD40_00E4 ETH1_TSAD ETH1_RSAD ETH1_IMR ETH1_ISR ETH1_TMF0 ETH1_TMF1 ETH1_TMF2 ETH1_TMF3 ETH1_MII ETH1_CNR2 ETH1_MPC ETH1_TXCOL ETH1_RXER Ethernet1 transmit starting address descriptor Ethernet1 receive starting address descriptor Ethernet1 interrupt mask register Ethernet1 interrupt status register Ethernet1 type match filter 0 Ethernet1 type match filter 1 Ethernet1 type match filter 2 Ethernet1 type match filter 3 Ethernet1 MII access register Ethernet1 control register 2 Ethernet1 mismatch packet counter Ethernet1 transmit collision counter Ethernet1 receive error count
WLAN_ID WLAN ID WLAN_MAR WLAN multicast register WLAN_ TSFTR WLAN timing synchronization function timer register WLAN_ TLPDA WLAN transmit low priority descriptors start address WLAN_ TNPDA WLAN transmit normal priority descriptors start address WLAN_ THPDA WLAN transmit high priority descriptors start address WLAN_ BRSR WLAN basic rate set register WLAN_ BSSID WLAN basic service Set ID WLAN_ CR WLAN command register WLAN_IMR WLAN interrupt mask register WLAN_ISR WLAN interrupt status register WLAN_TCR WLAN transmit configuration register WLAN_RCR WLAN receive configuration register WLAN_TINT WLAN timer interrupt register WLAN_ TBDA WLAN transmit beacon descriptor start address WLAN_CR WLAN command register WLAN_CONFIG0 WLAN configuration register 0 WLAN_CONFIG2 WLAN configuration register 2 WLAN_ANAPARM WLAN analog parameter WLAN_MSR WLAN media status register WLAN_CONFIG3 WLAN configuration register 3 WLAN_CONFIG4 WLAN configuration register 4 WLAN_TESTR WLAN test mode register WLAN_SCR WLAN security configuration register WLAN_BCNITV WLAN beacon interval register WLAN_ATIMWND WLAN ATIM window register WLAN_BINTRITV WLAN beacon interrupt interval register WLAN_ATIMTRITV WLAN ATIM interrupt interval register WLAN_PHYDELAY WLAN PHY delay register WLAN_CRC16ERR WLAN CRC16 error count WLAN_PHYADDR WLAN PHY address register WLAN_PHYDATAW WLAN write data to PHY WLAN_PHYDATAR WLAN read data from PHY WLAN_PHYCFG WLAN PHY configuration register WLAN_DK0 WLAN default key 0 register WLAN_DK1 WLAN default key 1 register WLAN_DK2 WLAN default key 2 register WLAN_DK3 WLAN default key 3 register WLAN_CONFIG5 WLAN configuration register 5 WLAN_TPPOLL WLAN transmit priority polling register WLAN_CWR WLAN contention window register WLAN_RETRYCTR WLAN retry count register WLAN_RDSAR WLAN receive descriptor start address register
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RTL8181
0xBD40_0100 0xBD40_0106 0xBD40_0116 WLAN_KMAR WLAN_KMKEY WLAN_KMC WLAN key map address register WLAN key map key value WLAN key map configuration
5. System Configuration
GPIO pin for system configuration GPIOB pin Power on Latch Value 9-6 1111 other values are reserved 11,10 13 01 11 other values are reserved 1 0 15-14 1,0 Reserved Reserved Operating setting CPU=200,MEM=100 if Memory use asynchronous mode JTAG mode Normal mode (wlan LED) Power on default 1,1,1,1
1,1
Memory clock use 1 asynchronous mode. Synchronous mode,the MEM clock same as CPU clock Reserved Reserved 1,1
System Control Register Set Virtual address Size (byte) Name 0xBD01_0100 4 BRIDGE_R EG 0xBD01_0104 4 PLLMN_R EG 0xBD01_0108 1 MEM_REG 0xBD01_0109 1 CPU_REG
Description WLAN, Eherernet0, Ethernet1 and PCI bridge configuration register RTL8181 DPLL parameter RTL8181 Memory clock rate RTL8181 CPU clock rate
Bridge Control Register (BRIDGE_REG) Since the Lexra bus clock rate is fast than the network device, it needs a bus bridge between the CPU and device (i.e., Ethernet and Wireless LAN controller). Also, this bridge is existed between CPU and PCI bridge. Bit Bit Name Description R/W InitVal 2-0 NIC0CKR Bus clock to NIC0 clock ratio. 001= 1:2, R/W 011 011=1:4,101=1:6,111=1:8 ,other value reserved. The NIC0 and NIC1 maximum clock is 50MHz. 3 NIC0CKREN NIC0CKR write enable R/W 0 6-4 Reserved 7 DISNIC0B Disable NIC0,0 enable NIC0, 1 disable NIC0 R/W 0 10-8 NIC1CKR Bus clock to NIC1 clock ratio. 001= 1:2, R/W 011 011=1:4,101=1:6,111=1:8 ,other value reserved 11 NIC1CKREN NIC0CKR write enable R/W 0 14-12 Reserved R/W 0 15 DISNIC1B Disable NIC1,0 enable NIC1, 1 disable NIC1 R/W 0 18-16 PCICLKR Bus clock to PCI clock ratio. 000=1:1,001= R/W 101 1:2,010=1:3,011=1:4,100=1:5,101=1:6,110=1: 7,111=1:8. The PCI maximum clock is 50MHz. 19 PCICKREN PCICLKR write enable R/W 0 20 LXPCI The external Bus is PCI or Lexra(debug R/W 1 mode).0 Lexra, 1 PCI. 21 PCI2ENB The second PCI bus enable. 0 enable second R/W 1 PCI device,1 disable second PCI device 22 Reserved
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RTL8181
23 26-24 Disable PCI bridge,0 enabe PCI bridge,1 R/W disable PCI bridge WLANCKR Bus clock to WLAN clock ratio. 000=1:1,001= R/W 1:2,010=1:3,011=1:4,100=1:5,101=1:6,110=1: 7,111=1:8. The WLAN maximum clock is 40MHz. WLANCKRE WLANCKR write enable R/W N Reserved DISWLANB Disable WLAN, 0 enabe WLAN,1 disable R/W WLAN DISPCIB 0 101
27 30-28 31
0 0
DPLL M,N parameter Register (PLLMN_REG) The DPLL clock rate is setting by this equation: 44MHz*(M+1)/(N+1) Bit Bit Name Description 4-0 NDIV DPLL N parameter 7-5 Reserved 13-8 MDIV DPLL M parameter 14 MNEN MDIV and NDIV write enable,0 disable ,1 enable 31-15 Reserved -
R/W R/W R/W R/W -
InitVal 00011 10011 0 0
Memory parameterRegister (MEM _REG) Bit Bit Name Description 2-0 MEMDIV MEM clock ,000:DPLL/1, 001: DPLL/1.5, 010: DPLL/2,011:DPLL/2.5, 100:DPLL/3,101:DPLL/4, 110:DPLL/6, 111:DPLL/8 3 MEMDIVEN Enable MEMDIV writw,0 disable ,1 enable 7-4 Reserved CPU parameter Register (CPU_REG) Bit Bit Name Description 2-0 CPUDIV CPU clock ,000:DPLL/1, 001: DPLL/1.5, 010: DPLL/2,011:DPLL/2.5, 100:DPLL/3,101:DPLL/4, 110:DPLL/6, 111:DPLL/8 3 CPUDIVEN Enable CPUDIV writw,0 disable ,1 enable 7-4 Reserved -
R/W R/W
InitVal 000
R/W -
0 -
R/W R/W
InitVal 000
R/W -
0 -
6. Interrupt Controller
RTL8181 provides six hardware- interrupt inputs IRQ0-IRQ5 internally. Some devices will share the same IRQ signal. Following table displays the IRQ map used by devices: IRQ Number 0 1 2 3 4 5 Interrupt Source Timer/Counter interrupt GPIO/LBC interrupt WLAN interrupt UART/PCI interrupt Ethernet0 interrupt Ethernet1 interrupt
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There are two registers for the interrupt control. The GIMR register can enable/disable the interrupt source. The GISR shows the pending interrupt status. Interrupt Control Register Set Virtual address Size (byte) Name 0xBD01_0000 2 GIMR 0xBD01_0004 2 GISR
Description Global interrupt mask register Global interrupt status register
Global Interrupt Mask Register (GIMR) Bit Bit Name Description 0 TCIE Timers/Counters interrupt enable. 0: Disable, 1: Enable 1 GPIOIE GPIO interrupt enable. 0: Disable, 1: Enable 2 WLAIE WLAN controller interrupt enable. 0: Disable, 1: Enable 3 UARTIE UART interrupt enable. 0: Disable 1: Enable 4 ETH0IE Ethernet0 interrupt enable. 0: Disable, 1: Enable 5 ETH1IE Ethernet1 interrupt enable. 0: Disable, 1: Enable 6 PCIIE PCI interrupt enable. 0: Disable, 1: Enable 7 Reserved 8 LBC1E LBC time-out interrupt enable. 0: Disable, 1: Enable Global Interrupt Status Register (GISR) Bit Bit Name Description 0 TCIP Timers/Counters interrupt pending flag. 0: no pending, 1: pending 1 GPIOIP GPIO interrupt pending flag. 0: no pending, 1: pending 2 WLAIP WLAN controller interrupt pending flag. 0: no pending, 1: pending 3 UARTIP UARTI interrupt pending flag. 0: no pending, 1: pending 4 ETH0IP Ethernet0 interrupt pending flag. 0: no pending, 1: pending 5 ETH1IP Ethernet1 interrupt pending flag. 0: no pending, 1: pending 6 PCIIP PCI interrupt pending flag. 0: no pending, 1: pending 7 Reserved 8 LBCIP LBC time-out interrupt pending flag. 0: no pending, 1: pending
R/W R/W R/W R/W R/W R/W R/W R/W
InitVal 0 0 0 0 0 0 0
R/W
0
R/W R R R R R R R
InitVal 0 0 0 0 0 0 0
R
0
7. Memory Controller
RTL8181 provides a memory control module that could access external asynchronous SDRAM and flash memory. RTL8181 could interface to PC100 or PC133-compliant SDRAM, and supports with auto-refresh mode, which requires 4096-cycle refresh in 64 ms. The SDRAM could be accessed in two banks (CS0#, and CS1#), and its size and timing are configurable in register. The data width of SDRAM could be chosen as 16-bit or 32-bit in register as well. If 32-bit is configured, 2 banks of 16-bit SDRAM may be used to expand its data width to 32 bits or use one bank of 32-bit SDRAM is allowable. 18
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RTL8181
Besides, RTL8181could also supports two banks (F_CS0# and F_CS1#) access for flash memory. The system will always boot up from bank 0. The boot bank is mapped to KSEG1 and its beginning physical address at 0xBFC0_0000 (physical address: 0x1FC0_0000). Bank 1 flash memory will be mapped to the address "0x1FC0_000 + flash size". The flash size is configurable from 1M to 8M bytes for each bank. If flash size set to 4M or 8M the 0xBFC0_0000 still map the first 4M bytes of flash. There will have a new memory mapping from 0xBE00_0000. The 0xBE00_0000 mapped to the bank 0 byte 0. Memory Conf iguration Register Set Virtual address Size (byte) Name Description 0xBD01_1000 4 MCR Memory Configuration Register 0xBD01_1004 4 MTCR0 Memory Timing Configuration Register 0 0xBD01_1008 4 MTCR1 Memory Timing Configuration Register 1 Note: These three registers should be accessed in double word. Memory Configuration Register (MCR) Bit Bit Name Description .31-30 FLSIZE Flash size respective to one bank (byte). 00: 1M, 01: 2M, 10: 4M, 11:8M 29-28 SDRSIZE SDRAM size respective to one bank (bit). 00: 512Kx16x2, 01: 1Mx16x4, 10: 2Mx16x4, 11:Reserved 27 CAS CAS Latency 0: Latency=2, 1: Latency=3 26-25 FLBK0BW Flash bank 0 bus width. 01: 16 bit 24-23 FLBK1BW Flash bank 1 bus width 00 11 10: reserved, 01: 16 bit 22-21 Reserved 20 SDBUSWID SDRAM bus width 0: 16 bit, 1: 32 bit 19 MCK2LCK Memory clock mode.Power on latch from GPIOB[13].1:Memory clock is the same as CPU clock. 0:memory clock following the power on latch from SYSCFG[3-0].
R/W R/W R/W WR R W/R
InitVal 11 01 0
01
W/R R
1 0
18-16
BUSCLK
15-0
Reserved
Bus Clock to control auto-refresh timing 000:200, 001:100, 010:50, 011:25, 100:12.5, 101:6.25 110: 3.125, 111: 1.5625 MHz Must be set to bit value 00.
R/W
000
R/W
00
Memory Timing Configuration Register 0 (MTCR0) Bit Bit Name Description 31-28 CE0T_CS The timing interval between F_CE0# to WR# Basic unit, 2*clock cycle "0000" means 1 unit (2 clock cycles) 27-24 CE0T_WP The timing interval for WR# to be pulled-low Basic unit, 2*clock cycle "0000" means 1 unit (2 clock cycles) 23-20 CE1T_CS The timing interval between F_CE1# to WR# Basic unit, 2*clock cycle "0000" means 1 unit (2 clock cycles) 19-16 CE1T_WP The timing interval for WR# to be pulled-low Basic unit, 2*clock cycle "0000" means 1 unit (2 clock cycles) 15-0 Reserved Note: The clock cycle is based memory clock. Memory Timing Configuration Register 1 (MTCR1) Bit Bit Name Description
R/W R/W
InitVal 1111
R/W
1111
R/W R/W
1111 1111
R/W
InitVal
CONFIDENTIAL
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v1.0
RTL8181
CE23T_RP=T_RCD T_RP and T_RCD timing parameter Basic unit, 1*clock cycle "0000" means 1 unit (1 clock cycle) 9-5 CE23T_RAS T_RAS timing parameter Basic unit, 1*clock cycle "0000" means 1 unit (1 clock cycle) 4-0 CE23T_RFC T_RFC timing parameter for refresh interval Basic unit, 1*clock cycle "0000" means 1 unit (1 clock cycle) Note: The clock cycle is based memory clock. The SDRAM timing: 12-10 R/W R/W 111 11111
R/W
11111
The write access timing of flash memory:
A[20..0] F_CE0# OE# Twp Tcs WR# D[n..0]
CONFIDENTIAL
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v1.0
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The read access timing of flash memory:
A[20..0] F_CE0# WE# OE# D[n..0]
8. Ethernet Controller
There are two 10/100M Ethernet MAC embedded in RTL8181. The Ethernet device has bus master capability, which will move packets between SDRAM and Ethernet controller through DMA mechanism. Thus, it could offload the CPU loading and get better performance. Besides, it also supports full-duplex operation, making possible 200Mbps bandwidth at no additional cost. Ethernet 0 Register Set (LAN PORT) Virtual Address Size (byte) Name 0xBD20_0000 4 ETH0_CNR1 0xBD20_0004 6 ETH0_ID 0xBD20_000C 8 ETH0_MAR 0xBD20_0014 4 ETH0_TSAD 0xBD20_0018 0xBD20_0020 0xBD20_0024 0xBD20_0028 0xBD20_002C 0xBD20_0030 0xBD20_0034 0xBD20_0038 0xBD20_003C 0xBD20_0040 0xBD20_0080 4 2 2 4 4 4 4 4 4 16 3
0xBD20_0084
2
0xBD20_0088
2
Description Control register 1 NIC ID Multicast register Transmit Starting Logic Address of Descriptor ETH0_RSAD Receive Starting Logic Address of Descriptor ETH0_IMR Ethernet0 Interrupt Mask Register ETH0_ISR Ethernet0 Interrupt Status Register ETH0_TMF0 Type match filter 0 register ETH0_TMF1 Type match filter 1 register ETH0_TMF2 Type match filter 2 register ETH0_TMF3 Type match filter 3 register ETH0_MII MII access register ETH0_CNR2 NIC control register 2 ETH0_UAR Unicast address filter register ETH0_MPC Indicates the number of packets discarded due to rx FIFO overflow. It is a 24-bit counter. It is cleared to zero by read command. ETH0_TXCOL Transmit collision counter. This 16-bit counter increments by 1 for every collision event. It rolls over when becomes full. It is cleared to zero by read command. ETH0_RXER Receive error count. This 16-bit counter increments by 1 for each valid packet received . It is cleared to zero by read command.
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
Ethernet 1 Register Set (WAN PORT) Virtual Address Size (byte) Name 0xBD30_0000 4 ETH1_CNR1 0xBD30_0004 6 ETH1_ID 0xBD30_000C 8 ETH1_MAR
Description Control register 1 NIC ID Multicast register
Access R/W R/W R/W
CONFIDENTIAL
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v1.0
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0xBD30_0014 0xBD30_0018 0xBD30_0020 0xBD30_0024 0xBD30_0028 0xBD30_002C 0xBD30_0030 0xBD30_0034 0xBD30_0038 0xBD30_003C 0xBD30_0080 4 4 2 2 4 4 4 4 4 4 3 Transmit Starting Logic Address of Descriptor ETH1_RSAD Receive Starting Logic Address of Descriptor ETH1_IMR Ethernet0 Interrupt Mask Register ETH1_ISR Ethernet0 Interrupt Status Register ETH1_TMF0 Type match filter 0 register ETH1_TMF1 Type match filter 1 register ETH1_TMF2 Type match filter 2 register ETH1_TMF3 Type match filter 3 register ETH1_MII MII access register ETH1_CNR2 NIC control register 2 ETH1_MPC Ind icates the number of packets discarded due to rx FIFO overflow. It is a 24-bit counter. It is cleared to zero by read command. ETH1_TXCOL Transmit collision counter. This 16-bit counter increments by 1 for every collision event. It rolls over when becomes full. It is cleared to zero by read command. ETH1_RXER Receive error count. This 16-bit counter increments by 1 for each valid packet received . It is cleared to zero by read command. ETH1_TSAD R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
0xBD30_0084
2
R
0xBD30_008C
2
R
Ethernet Control Register 1 (ETH0_CNR1, ETH1_CNR1) Bit Bit Name Description 31-29 RXBLEN Rx Burst length on Lexra bus. 000 - 010 = 64 bytes 28-26 TXBLEN Tx Burst length on Lexra bus. 000 = 16 bytes 001 = 32 bytes 010 = 64 bytes 25 FIFOAddrPtr FIFO Address Pointer: (Realtek internal use only to test FIFO SRAM) 0: Both Rx and Tx FIFO address pointers are updated in ascending way from 0 and upwards. The initial FIFO address pointer is 0. 1: Both Rx and Tx FIFO address pointers are updated in descending way from 1FFh and downwards. The initial FIFO address pointer is 1FFh. 24 TDFN Tx Descriptor Fetch Notify. Set this bit to notify the NIC to fetch the Tx descriptors. The NIC will clear this bit automatically after all packets have been transmitted. Writing 0 to this bit has no effect. 20 RST Reset. A soft reset which disable the transmitter and receiver, re- initializes the FIFOs, and buffer pointer to the initial value. 19 RE Receiver enable. 18 TE Transmitter enable. 17 TxFCE Transmit flow control enable. 16 RxFCE Receive flow control enable 15 Reserved 14 RxVLAN Receive VLAN un-tagging enable 13 RxChkSum Receive checksum offload enable
R/W InitVal R/W 000 R/W 000
R/W 0
W
0
W
0
0 0 0 0 0 R/W 0 R/W 0
R/W R/W R/W R/W
CONFIDENTIAL
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v1.0
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12 FSWInt Forced software interrupt. Writing 1 to this bit will trigger an interrupt, and the SWIP bit will be set. The NIC will clear this bit automatically after SWIP bit is cleared. Writing 0 to this bit has no effect. Loopback test. Setting both bits will route all transmit traffic from Tx FIFO to Rx FIFO 00: normal operation 01, 10: reserved 11: loopback mode No CRC. 0: CRC appended 1: no CRC appended Accept error packets Accept Broadcast packets Accept Multicast packets Accept Physical address Matched packets Accept All Physical packets W
11-10
LBK[1:0]
R/W 00
9
NoCRC
R/W 0
8 7 6 5 4 3 2 1
AER AB AM APM AAP ATM AR ALEN
R/W 0 R/W R/W R/W R/W 0 0 0 0
Accept Type match packets. This bit enables the R/W 0 qualification of types of received packets. Accept runt packets R/W 0 Accept length specific packets. This bit is effective R/W 0 when ATM bit is set. 0: filter length specific packets. 1: accept length specific packets.
Ethernet Control Register 2 (ETH0_CNR2, ETH1_CNR2) Bit Bit Name Description 16 UAEN Unicast address filter enable (note). 0: disabled. 1: enabled. 15 TXPON Send Pause On packet. Write "1" to send Pause On packet. 14 TXPOFF Send Pause Off packet. Write "1" to send Pause Off packet. 13 TXPF Send Pause flag. Set, when NIC sends Pause-On packet. Reset, when NIC sends Pause-Off packet. 12 RXPF Receive Pause Flag: Set, when NIC is in backoff state because a pause packet received. Reset, when pause state is clear. 11-8 PTMASK[3:0] Pause time mask. These bits mask the most significant four bits of pause time 0xFFFF used for a PAUSE packet. For example, if PTMASK[3:0 ] is set to 0x01, a PAUSE packet with pause time 0x1FFF will be sent when descriptor unavailable condition occurs. 6-4 IFG[2:0] InterFrameGap Time: This field allows the user to adjust the interframe gap time longer than the standard: 9.6 us for 10Mbps, 960 ns for 100Mbps. The time can be programmed from 9.6 us to 14.4 us (10Mbps) and 960ns to 1440ns (100Mbps). The formula for the inter frame gap is 011: 9.6us/ 960ns 100: 9.6+4*0.1us/ 960+4*10ns 101: 9.6+8*0.1us/ 960+8*10ns 110: 9.6+12*0.1us/ 960+12*10ns 111: 9.6+16*0.1us/ 960+16*10ns 23
R/W InitVal R/W 0 W W R R 0 0 0 0
R/W 1111
R/W 011
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000: 9.6+20*0.1us/ 960+20*10ns 001: 9.6+24*0.1us/ 960+24*10ns 010: 9.6+48*0.1us/ 960+48*10ns R/W 0 3-0 TXRR[3:0] Tx Retry Count: These are used to specify additional transmission retries in multiple of 16(IEEE 802.3 CSMA/CD retry count). If the TXRR is set to 0, the transmitter will re-transmit 16 times before aborting due to excessive collisions. If the TXRR is set to a value greater than 0, the transmitter will re-transmit a number of times equals to the following formula before aborting: Total retries = 16 + (TXRR * 16) The TER bit in the ISR register or transmit descriptor will be set when the transmission fails and reaches to this specified retry co unt. Note: Bit UAEN is only existed in ETH0_CNR2 register. Unicast Address Filter Register (ETH0_UAR) Bit Bit Name Description R/W InitVal 127-0 UARTBL Unicast address hash table. If the `n' bit value is R/W 0 set `1', it implies the receiving frames which hash value with `n' will be indicated. Interrupt Mask Register (ETH0_IMR, ETH1_IMR) Bit Bit Name Description 9 LINKCHGIE Link status changed interrupt enable 8 RERIE Rx error interrupt enable 7 TERIE Tx error interrupt enable 6 ROKIE ROK interrupt enable. A descriptor reception is completed successfully. 5 TOKIE TOK interrupt enable. A descriptor transmission is completed successfully. 4 RFOVWIE Rx FIFO overflow interrupt enable 3 RDUIE Rx descriptor unavailable interrupt enable. Set when the Rx Descriptors have been exhausted. 2 Reserved 1 TDUIE Tx descriptor unavailable interrupt enable 0 SWIE Software interrupt enable Interrupt Status Register (ETH0_ISR, ETH1_ISR) Bit Bit Name Description 9 LINKCHGIP Link status changed interrupt pending flag. Write "1" to clear the interrupt. 8 RERIP Rx error interrupt pending flag. Write "1" to clear the interrupt. 7 TERIP Tx error interrupt enable flag. Write "1" to clear the interrupt. 6 ROKIP ROK interrupt pending. A descriptor reception is completed successfully. Write "1" to clear the interrupt. 5 TOKIP TOK interrupt pending. A descriptor transmission is completed successfully. Write "1" to clear the interrupt. 4 RFOVWIP Rx FIFO overflow interrupt pending Write "1" to clear the interrupt.. 3 RDUIP Rx descriptor unavailable interrupt pending. Set when the Rx Descriptors have been exhausted. Write "1" to clear the interrupt and it also trigger 24
R/W R/W R/W R/W R/W
InitVal 0 0 0 0
R/W 0 R/W 0 R/W 0
R/W 0 R/W 0
R/W InitVal R/W 0 R/W 0 R/W 0 R/W 0
R/W 0 R/W 0 R/W 0
CONFIDENTIAL
v1.0
RTL8181
NIC to send PAUSE 0x0000 packet. 2 1 0 Reserved TDUIP SWIP Tx descriptor unavailable interrupt pending flag. R/W 0 Write "1" to clear the interrupt. Software interrupt pending flag. Write "1" to clear R/W 0 the interrupt.
MII Access Register (ETH0_MII, ETH1_MII) Bit Bit Name Description 31-22 Reserved 21 MMIMODE Mode of MII management interface. (Realtek internal use only to test 3-port switch) 0 = auto mode. The NIC controls MDC and MDIO pins. Setting this bit will trigger an auto- negotiation if DisNway bit is cleared. 1 = manual mode. The software controls MDC and MDIO pins. 20-16 PHYAD[4:0] PHY address. 15 LinkCtrl Link control. 0: force link down. 1: force link up. 14 DplxCtrl Duplex control. When DuplexCtrl bit is cleared, this bit is read only. The NIC will poll its local PHY regularly. This bit will reflect the result of auto- negotiation from its local PHY. If FDuplex is set, this bit is writable. The software may program the bit and force the MII operates in full-duplex or half-duplex mode. 0: Force half-duplex mode. 1: Force full-duplex mode. 13 SpdCtrl Speed control. 0: 10Mbps 1: 100Mbps. 12 FlCtrl Flow control. 0:disable flow control. 1: enable flow control. 11 LinkSt Link status. This bit reflects the link status from its local PHY. 0: link down 1: link up 10 DuplexSt Duplex status. This bit reflects the duplex status from its local PHY. 0: half duplex 9 SpeedSt Speed status. This bit reflects the link speed from its local PHY. 0: 10Mbps 1: 100Mbps 8 FlCtrlSt Flow control status 0: flow control disabled 1: flow control enabled. 7-5 Reserved 4 DisNway Disable N-way 0: auto- negotiation mode.The local PHY will advertise its capability per the settings of DplxCtrl, SpdCtrl, and FlCtrl bits. 1: forced mode (disable N-way). The software may force MII operating mode by writing the corresponding value to the DplxCtrl, LinkCtrl, SpdCtrl,FlCtrl bits. 25
R/W InitVal R/W 0
R/W 0x01 R/W 0 R/W 1
R/W 1
R/W 0 R 0
R
0
R
0
R
0
R/W 0
CONFIDENTIAL
v1.0
RTL8181
3 MDM Management Data Mode: 0: MDIO pin is input. MDI bit reflects the state of MDIO pin. The default value is "0". 1: MDIO pin is output, and the state of MDIO pin reflects with MDO bit. MII Management Data-OUT: Used by the NIC to write data to the MDIO pin. MII Management Data-IN: Used by the NIC to read data from the MDIO pin. Management Data Clock: This bit reflects the state of MDC pin. R/W 0
2 1 0
MDO MDI MDC
R/W X R X
R/W 0
Transmit Descriptor
Tx Descriptor Format (before transmitting, OWN=1, LGSEN=0, Tx command mode 1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OEF L LRR WO S S G E E NR SSS = EVV 1 N = 0
R E S V
R E S V
R E S V
R E S V
R E S V
R E S V
I P C S
U D P C S
T C P C S
Offset 0 Frame_Length
Offset 4 VLAN_TAG
TAGC
RESV
Offset 8 TX_BUFFER_ADDRESS Offset 12 Dummy Byte Offset# 0 Bit# Bit Name Description 31 OWN When set, indicates that the descriptor is owned by NIC, and the data relative to this descriptor is ready to be transmitted. When cleared, indicates that the descriptor is owned by host system. NIC clears this bit when the relative buffer data is transmitted. In this case, OWN=1. End of descriptor Ring. When set, indicates that this is the last descriptor in descriptor ring. When NIC's internal transmit pointer reaches here, the pointer will return to the first descriptor of the descriptor ring after transmitting the data relative to this descriptor. First segment descriptor. When set, indicates that this is the first descriptor of a Tx packet, and this descriptor is pointing to the first segment of the packet. Last segment descriptor. When set, indicates that this is the last descriptor of a Tx packet, and this descriptor is pointing to the last segment of the packet. A command bit. TCP/IP-Large-send operation enables. Driver sets this bit to enable NIC to offload CPU operation for TCP/IP fragmentation. Reserved. A command bit. IP checksum offload. Driver sets this bit to ask NIC to offload IP checksum. A command bit. UDP checksum offload. Driver sets this bit to ask NIC to offload UDP checksum. A command bit. TCP checksum offload enable. Driver sets this bit to ask NIC to offload TCP checksum. 26
0
30
EOR
0 0
29 28
FS LS
0 0 0 0 0
27
LGSEN
26-19 18 17 16 IPCS UDPCS TCPCS
CONFIDENTIAL
v1.0
RTL8181
0 4 4 15-0 Frame_Le Transmit frame length. This field indicates the length in TX buffer, in ngth byte, to be transmitted 31-18 RSEV Reserved. VLAN tag control bits: 00: Packet remains unchanged when transmitting 10: Add TAG. 0x8100 (Ethernet encoded tag protocol ID, indicating that this is a IEEE 802.1Q VLAN packet) is inserted after source address, and 2 bytes are inserted after tag protocol ID from VLAN_TAG field in transmit descriptor. 15-0 VLAN_T The 2-byte VLAN_TAG contains information, from upper layer, of AG user priority, canonical format indicator, and VLAN ID. Please refer to IEEE 802.1Q for detailed VLAN tag information. 31-0 TxBuff Logic Address of transmission buffer. 17-16 TAGC
4
8
Tx Status Descriptor (after transmitting, OWN=0, Tx status mode) After having transmitted, the Tx descriptor turns to be a Tx status descriptor.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
O E F L R R U R T O L E CC3-0 WO S S E E N E E WN X NR SS F S SCKC = VV V F 0 TAGC RESV
Offset 0 Frame_Length
Offset 4 VLAN_TAG
Offset 8 TX_BUFFER_ADDRESS Offset 12 Dummy
Byte Offset# 0
Bit# Bit Name Description 31 OWN When set, indicates that the descriptor is owned by NIC. When clear indicates that the descriptor is owned by host system. NIC clears this bit when the relative buffer data is already transmitted. In this case, OWN=0. End of descriptor Ring. When set, indicates that this is the last descriptor in descriptor ring. When NIC's internal transmit pointer reaches here, the pointer will return to the first descriptor of the descriptor ring after transmitting the data relative to this descriptor. First segment descriptor. When set, indicates that this is the first descriptor of a Tx packet, and this descriptor is pointing to the first segment of the packet. Last segment descriptor. When set, indicates that this is the last descriptor of a Tx packet, and this des criptor is pointing to the last segment of the packet. Reserved. FIFO underrun. A status bit. NIC sets this bit to inform driver that FIFO underrun had ever occurred before this packet transmitted. Reserved. Transmit Error Summary. When set, indicates that at least one of the following errors occurred: OWC, EXC, LNKF. This bit is valid only when LS (Last segment bit) is set. 27
0
30
EOR
0
29
FS
0
28
LS
0 0 0 0
27-26 25 24 23 UNF TES
CONFIDENTIAL
v1.0
RTL8181
0 0 0 0 22 21 20 OWC LNKF EXC Out of Window Collision. A status bit. Out of window collision, When set, it means an "out-of-window" collision is encountered during transmitting packet. Link Failure. A status bit. NIC sets this bit to inform link failure to driver Excessive Collision. When set, indicates that the transmission was aborted owing to consecutive 16 collisions. Collision Counter. When Own bit =0, it 's a status field, A 4-bit collision counter, shows the total collision times before the packet was transmitted. Reserved.
19-16 CC3-0
0 0 4 4
23-16 -
15-0 Frame_Le Transmit frame length. This field indicates the length in TX buffer, in ngth byte, to be transmitted 31-18 RSEV Reserved. 17-16 TAGC VLAN tag control bits: 00: Packet remains unchanged when transmitting. 10: Add TAG. 0x8100 (Ethernet encoded tag protocol ID, indicating that this is an IEEE 802.1Q VLAN packet) is inserted after source address, and 2 bytes are inserted after tag protocol ID from VLAN_TAG field in transmit descriptor. 15-0 VLAN_T The 2-byte VLAN_TAG contains information, from upper layer, of AG user priority, canonical format indicator, and VLAN ID. Please refer to IEEE 802.1Q for detailed VLAN tag information. 31-0 TxBuff Logic Address of transmission buffer.
4
8
Reception Descriptor
Rx Command Descriptor (OWN=1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OE WO NR = 1 RESV
Offset 0 RESV Buffer_Size
T A V A
VLAN_TAG
Offset 4
Offset 8 RX_BUFFER_ADDRESS Offset 12 Dummy Bye Offset# 0 Bit# Bit Name 31 OWN Description When set, indicates that the descriptor is owned by NIC, and is ready to receive packet. The OWN bit is set by driver after having pre-allocated buffer at initialization, or the host has released the buffer to driver. In this case, OWN=1. End of Rx descriptor Ring. Set to 1 indicates that this descriptor is the last descriptor of Rx descriptor ring. Once NIC' internal s receive descriptor pointer reaches here, it will return to the first descriptor of Rx descriptor ring after this descriptor is used by packet reception.
0
30
EOR
CONFIDENTIAL
28
v1.0
RTL8181
0 0 29-13 12-0 Buffer_Size Reserved. This field indicate the receive r buffer size in bytes. Although the maximum buffer size is 8K bytes/buffer, the NIC purges all data after 4K bytes if the packet is larger than 4K-byte long. Reserved. Tag Available. When set, the received packet is an IEEE802.1Q VLAN TAG (0x8100) available packet. If the packet `s TAG is 0x8100, The NIC extracts four bytes from after source ID, sets TAVA bit to1, and moves the TAG value to this field in Rx descr iptor. Logic Address of receive buffer.
4 4 4
31-17 RSEV 16 TAVA
15-0 VLAN_TAG
8
31-0 RxBuff
Rx Status Descriptor (OWN=0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OEF L F M P BBF RRRCPP UT W O S S A A A A O O W E U R I I IP D C NR E R MR V V T S N C D D F P P = FF T 10 FF 0 T RESV A V A
Frame_Length
Offset 0
Offset 4 VLAN_TAG
Offset 8 RX_BUFFER_ADDRESS Offset 12 Dummy
Bye Offset# 0
Bit# Bit Name Description 31 OWN When set, indicates that the descriptor is owned by NIC. When cleared, indicates that the descriptor is owned by host system. NIC clears this bit when NIC has filled up this Rx buffer with a packet or part of a packet. In this case, OWN=0. End of Rx descriptor Ring. Set to 1 indicates that this descriptor is the last descriptor of Rx descriptor ring. Once NIC's internal receive descriptor pointer reaches here, it will return to the first descriptor of Rx descriptor ring after this descriptor is used by packet reception. First segment descriptor. When set, indicates that this is the first descriptor of a received packet, and this descriptor is pointing to the first segment of the packet. Last segment descriptor. When set, indicates that this is the last descriptor of a received packet, and this descriptor is pointing to the last segment of the packet. Frame Alignment Error. When set, indicates a frame alignment error has occurred on the received packet. The FAE packet is able to be received only when RCR_AER is set. Multicast Address packet Received: When set, indicates that a multicast packet is received Physical Address Matched. When set, indicates that the destination address of this Rx packet matches to the value in NIC 's ID registers. Broadcast Address Received. When set, indicates that a broadcast packet is received. BAR and MAR will not be set simultaneously.
0
30
EOR
0
29
FS
0
28
LS
0 0 0 0
27 26 25 24
FAE MAR PAM BAR
CONFIDENTIAL
29
v1.0
RTL8181
0 0 0 Buffer Overflow. When set, indicates that receive buffer has ever exhausted before this packet is received. 22 FOVF FIFO Overflow. When set, indicates that FIFO overflow has ever occurred before this packet is received. 21 RWT Receive Watchdog Timer expired. When set, indicates that the received packet length exceeds 1724 bytes, the receive watchdog timer will expire and stop receive engine. 20 RES Receive Error Summary. When set, indicates at least one of the following errors occurred: CRC, RUNT, RWT, FAE. This bit is valid only when LS(Last segment bit) is set 19 RUNT Runt packet. When set, indicates that the received packet length is smaller than 64 bytes. RUNT packet is able to be received only when RCR_AR is set. 18 CRC CRC error. When set, indicates that a CRC error has occurred on the received packet. A CRC-error packet can be received only when RCR_AER is set. 17-16 PDI[1:0] Protocol ID1, Protocol ID0 00: Non-IP 01: TCP/IP 10: UDP/IP 11: IP. 15 IPF When set, indicates IP checksum failure. 14 13 UDPF TCPF When set, indicates UDP checksum failure. When set, indicates TCP checksum failure. 23 BOVF
0
0
0 0
0 0 0 0 4 4 4 8
12-0 Frame_Le When OWN=0 and LS =1, it indicates the received packet length ngth including CRC, in bytes. 31-17 RSEV Reserved. 16 Tag Available. When set, the received packet is an IEEE802.1Q VLAN TAG (0x8100) available packet. 15-0 VLAN_T If the packet `s TAG is 0x8100, The NIC extrac ts four bytes from after AG source ID, sets TAVA bit to1, and moves the TAG value to this field in Rx descriptor. 31-0 RxBuff Logic Address of receive buffer. TAVA
9. UART Controller
RTL8181 provides a 16C550 compatible UART, which contains 16 byte FIFOs. In addition, auto flow control is provided, in which, auto-CTS mode (CTS controls transmitter) and auto-RTS mode (Receiver FIFO contents and threshold control RTS) are both supported. The baud rate is programmable and allows division of any input reference clock by 1 to (2^16-1) and generates an internal 16x clock. RTL8181 provides fully programmable serial interface, which can be configured to support 7,8 bit characters, even, odd, no parity generation and detection, and 1 or 2 stop bit generation. Last, full y prioritized interrupt control and loopback functionality for diagnostic capability are also provided. The clock source is 22MHz. UART Register Set Virtual address Size (byte) Name 0xBD01_00C3 1 UART_RBR 0xBD01_00C3 1 UART_THR 0xBD01_00C3 1 UART_DLL 0xBD01_00C7 1 UART_IER 0xBD01_00C7 1 UART_DLM 0xBD01_00CB 1 UART_IIR 0xBD01_00CB 1 UART_FCR 0xBD01_00CF 1 UART_LCR 0xBD01_00D3 1 UART_MCR
Description Receiver buffer register. (DLAB=0) Transmitter holding register. (DLAB=0) Divisor latch LSB. (DLAB=1) Interrupt enable register. (DLAB=0) Divisor latch MSB. (DLAB=1) Interrupt identification register. FIFO control register Line control register Modem control register
Access R W R/W R/W R/W R W R/W R/W
CONFIDENTIAL
30
v1.0
RTL8181
0xBD01_00D7 1 0xBD01_00DB 1 0xBD01_00DF 1 UART_LSR Line status register UART_MSR Modem status register UART_SCR Scratch register R/W R/W R/W
Interrupt Enable Register (UART_IER) Bit Bit Name Description 7-6 Reserved 5 ELP Low power mode enable 3 EDSSI Enable modem status registe r interrupt 4 ESLP Sleep mode enable 2 ELSI Enable receiver line status interrupt 1 ETBEI Enable transmitter holding register empty interrupt 0 ERBI Enable received data available interrupt Interrupt Identification Register (UART_IIR) Bit Bit Name Description 7:5 FIFO64[2:0] 000 = no FIFO 110 = 16-byte FIFO 4 Reserved 3:1 0 IID[2:0] IPND Interrupt ID. IID[1:0] indicates the interrupt priority. Interrupt pending 0 = interrupt pending
R/W R/W R/W R/W R/W R/W R/W
InitVal 0 0 0 0 0 0
R/W R R R R
InitVal 110 0 000 0
Interrupt Priority Interrupt Priority Identification Register level Bit3 Bit2 Bit1 Bit0 0 0 0 1 None 0 1 1 0 1 0 1 1 1 0 0 0 0 2 2
Interrupt type
Interrupt source
Interrupt reset method None Read LSR Read RBR.
None Receiver line status Received data available Character time-out indication
None Overrun, parity, framing errors or break DR bit is set.
0 0
0 0
1 0
0 0
3 4
No characters have been Read RBR removed from or input to FIFO during the last character times and at 1 character in it. Transmitter THRE bit set. Reading IIR or write holding register THR empty Modem status CTS#,DSR#,RI#,DCD# Reading MSR
FIFO Control Register (UART_FCR) Bit Bit Name Description 7-6 RTRG[1:0] Receiver trigger level Trigger level: 16-byte 00 = 01 01 = 04 10 = 08 11 = 14 3-5 Reserved 2 1 0 TFRST RFRST EFIFO
R/W W
InitVal 11
Transmitter FIFO reset. Writes 1 to clear the W transmitter FIFO. Receiver FIFO reset. Writes 1 to clear the receiver W FIFO. Enable FIFO. When this bit is set, enable the W 31
0 0 0
CONFIDENTIAL
v1.0
RTL8181
transmitter and receiver FIFOs. Changing this bit clears the FIFOs. Line Control Register (UART_LCR) Bit Bit Name Description 7 DLAB Divisor latch access bit. 6 BRK Break control. Set this bit force TXD to the spacing (low) state.(break) Clear this bit to disable break condition. 5-4 EPS[1:0] Even parity select 00 = odd parity 01 = even parity 10 = mark parity 11 = space parity 3 PEN Parity enable 2 STB Number of stop bits 0 = 1 bit 1 = 2 bits 1-0 WLS[1:0] Word length select 10 = 7 bits 11 = 8 bits Modem Control Register (UART_MCR) Bit Bit Name Description 7-6 Reserved 5 AFE Auto flow control enable 4 LOOP Loopback 2-3 Reserved 1 RTS Request to send 0 = Set RTS# high 1 = Set RTS# low 0 Reserved Line Status Register (UART_LSR) Bit Bit Name Description 7 RFE Errors in receiver FIFO. At least one parity, framing and break error in the FIFO. 6 TEMT Transmitter empty Character mode: both THR and TSR are empty. FIFO mode: both transmitter FIFO and TSR are empty 5 THRE Transmitter holding register empty. Character mode: THR is empty. FIFO mode: transmitter FIFO is empty 4 BI Break interrupt indicator 3 FE Framing error 2 PE Parity error 1 OE Overrun error. An overrun occurs when the receiver FIFO is full and the next character is completely received in the receiver shift register. An OE is indicated. The character in the shift register will be overwritten. 0 DR Data ready. Character mode: data ready in RBR FIFO mode: receiver FIFO is not empty. Modem Status Register (UART_MSR) Bit Bit Name Description 32
R/W R/W R/W
InitVal 0 0
R/W
0
R/W R/W
0 0
R/W
11
R/W R/W R/W R/W
InitVal 0 0 0
R/W R R
InitVal 0 0
R
0
R R R R
0 0 0 0
R
0
R/W
InitVal
CONFIDENTIAL
v1.0
RTL8181
7 6 5 4 DCD RI DSR CTS In loopback mode, returns the bit 2 of MCR. In normal mode, returns 1. In loopback mode, returns the bit 3 of MCR. In normal mode, returns 0. In loopback mode, returns the bit 0 of MCR In normal mode, returns 1. Clear to send. 0 = CTS# detected high 1 = CTS# detected low Reserved Delta clear to send. CTS# signal transits. R R R R 1 0 1 0
3-1 0
? CTS
R
0
10. Timer & Watchdog
There are four sets of hardware timer and one watchdog timer. Each timer can be configured as timer mode or counter mode. No matter counter or timer mode, the time value will be counted down from initial value to zero, which value is subtracted by one in every timer clock. When configured as timer mode, the source of timer clock could be configured to use base clock directly, or based on the base clock divided by a configurable register value - CDBR, which way is called as Basic timer. When the value is reaching to zero, the timer is stopped and an interrupt will be issued in counter mode. If configured as timer mode, beside to issue an interrupt, the time value will be reset to its initial value, and then count down timer be operated continuously, and an interrupt will be issued periodically whenever the count down value reaches to zero. When watchdog timer is enabled, it will cause the system reset when time out occurred. The time out interval could be selected from register, the time unit value is based on base clock divided by the base value, which is same used by timer. Timer & Watchdog Register Set Virtual address Size (byte) Name 0xBD01_0050 2 TCCNR 0xBD01_0054 1 TCIR 0xBD01_0058 1 CBDR 0xBD01_005C 2 WDTCNR 0xBD01_0060 3 TC0DATA 0xBD01_0064 0xBD01_0068 0xBD01_006C 0xBD01_0070 0xBD01_0074 0xBD01_0078 0xBD01_007C 3 4 4 3 3 4 4
Description Timer/Counter control register Timer/Counter interrupt register Clock division base register Watchdog timer control register Timer/Counter 0 data register. It specifies the time-out duration. TC1DATA Timer/Counter 1 data register. It specifies the time-out duration. TC2DATA Timer/Counter 2 data register. It specifies the time-out duration. TC3DATA Timer/Counter 3 data registe r. It specifies the time-out duration. TC0CNT Timer/Counter 0 count register TC1CNT Timer/Counter 1 count register TC2CNT Timer/Counter 2 count register TC3CNT Timer/Counter 3 count register
Access R/W R/W R/W R/W R/W R/W R/W R/W R R R R
Timer/Counter 0 Data register (TC0CNT) Bit Bit Name Description 23-0 TC0Value[23:0] The timer or counter initial value Timer/Counter 1 Data register (TC1CNT) Bit Bit Name Description 23-0 TC1Value[23:0] The timer or counter initial value Timer/Counter 2 Data register (TC2CNT) Bit Bit Name Description 31-0 TC2Value[31:0] The timer or counter initial value
R/W R/W
InitVal
R/W R/W
InitVal
R/W R/W
InitVal
CONFIDENTIAL
33
v1.0
RTL8181
Timer/Counter 3 Data register (TC3CNT) Bit Bit Name Description 31-0 TC3Value[31:0] The timer or counter initial value Timer/Counter Control register (TCCNR) Bit Bit Name Description 11 TC3Src Timer/Counter 3 clock source 0=Base clock 1=Basic timer 10 TC2Src Timer/Counter 2 clock source 0=Base clock 1=Basic timer 9 TC1Src Timer/Counter 1 clock source 0=Base clock 1=Basic timer 8 TC0Src Timer/Counter 0 clock source 0=Base clock 1=Basic timer 7 TC3Mode Timer/Counter 3 mode 0=counter mode 1=timer mode 6 TC3En Timer/Counter 3 enable 5 TC2Mode Timer/Counter 2 mode 0=counter mode 1=timer mode 4 TC2En Timer/Counter 2 enable 3 TC1Mode Timer/Counter 1 mode 0=counter mode 1=timer mode 2 TC1En Timer/Counter 1 enable 1 TC0Mode Timer/Counter 0 mode 0=counter mode 1=timer mode 0 TC0En Timer/Counter 0 enable Timer/Counter Interrupt Register (TCIR) Bit Bit Name Description 7 TC3IP Timer/Counter 3 interrupt pending. Write "1" to clear the interrupt. 6 TC2IP Timer/Counter 2 interrupt pending. Write "1" to clear the interrupt. 5 TC1IP Timer/Counter 1 interrupt pending. Write "1" to clear the interrupt. 4 TC0IP Timer/Counter 0 interrupt pending. Write "1" to clear the interrupt. 3 TC3IE Timer/Counter 3 interrupt enable 2 TC2IE Timer/Counter 2 interrupt enable 1 TC1IE Timer/Counter 1 interrupt enable 0 TC0IE Timer/Counter 0 interrupt enable
R/W R/W
InitVal
R/W R/W
InitVal 0
R/W
0
R/W R/W
0 0
R/W
0
R/W R/W
0 0
R/W R/W R/W R/W
0 0 0 0
R/W
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
InitVal 0 0 0 0 0 0 0 0
Clock Division Base Register (CDBR) Bit Bit Name Description R/W 15-0 DivFactor The divided factor of clock source. If DivFactor is R/W N, the watchdag timer divide by N+1.This value could not be 0 in timer mode or watchdog. The clock source is 22MHz. Watchdog Control Register (WDTCNR) 34
InitVal 0
CONFIDENTIAL
v1.0
RTL8181
Bit 10-9 Bit Name OVSEL[1:0] Description Overflow select. These bits specify the overflow condition when the watchdog timer counts to the value. 00 = 213 01 = 214 10 = 215 11 = 2 16 Watchdog clear. Write a 1 to clear the watchdog counter. It is auto cleared after the write. Watchdog enable. When these bits are set to 0xA5, the watchdog timer stops. Other value can enable the watchdog timer and cause a system reset when an overflow signal occurs. R/W R/W InitVal 00
8 7-0
WDTCLR WDTE[7:0]
W W
0 0xA5
11. GPIO Control
RTL8181 provides two sets of GPIO pins - PortA and PortB . PortA has 16 pins and PortB has 16 pins. Every GPIO pin can be configured as input or output pins via register PA(B)DIR. Register PA(B)DATA could be used to control the signals (high or low) of GPIO pins. Because the GPIO pins might be shared with some peripheral pins, the PA(B)CNR can control the attribute of the shared pins. Besides, PortB GPIO sets can be used to generate interrupt via PBIMR , and the interrupt status is shown in PBISR. GPIO Register Set Virtual address Size (byte) Name 0xBD01_0040 4 PABDIR 0xBD01_0044 4 PABDAT A 0xBD01_0048 4 PBIMR 0xBD01_004C 4 PBISR
Description Port A/B direction register Port A/B data register Port B interrupt mask register Port B interrupt register
Access R/W R/W R/W R
Port A,B Direction Register (PADIR , PBDIR) Bit Bit Name Description 31-16 DRCA[15:0] Pin direction configuration of Port A 0 = configured as input pin 1 = configured as output pin 15-0 DRCB[15:0] Pin direction configuration of Port B 0 = configured as input pin 1 = configured as output pin Port A,B DATA Register (PADATA, PBDATA) Bit Bit Name Description 31-16 DATAA[15:0] Pin data of Port A 15-0 DATAB[15:0] Pin data of Port B
R/W R/W
InitVal 00
R/W
00
R/W R/W R/W
InitVal 00 00
Port B Interrupt Mask Register (PBIMR) Bit Bit Name Description 1-0 PB0IM[1:0] PortB.0 interrupt mode 00 = disable interrupt 01 = enable falling edge interrupt 10 = enable rising edge interrupt 11 = enable both falling or rising edge interrupt 3-2 PB1IM[1:0] PortB.1 interrupt mode 00 = disable interrupt 01 = enable falling edge interrupt 35
R/W R/W
InitVal 00
R/W
00
CONFIDENTIAL
v1.0
RTL8181
10 = enable rising edge interrupt 11 = enable both falling or rising edge interrupt PortB.2 interrupt mode 00 = disable interrupt 01 = enable falling edge interrupt 10 = enable rising edge interrupt 11 = enable both falling or rising edge interrupt PortB.3 interrupt mode 00 = disable interrupt 01 = enable falling edge interrupt 10 = enable rising edge interrupt 11 = enable both falling or rising edge interrupt PortB.4 interrupt mode 00 = disable interrupt 01 = enable falling edge interrupt 10 = enable rising edge interrupt 11 = enable both falling or rising edge interrupt PortB.5 interrupt mode 00 = disable interrupt 01 = enable falling edge interrupt 10 = enable rising edge interrupt 11 = enable both falling or rising edge interrupt PortB.6 interrupt mode 00 = disable interrupt 01 = enable falling edge interrupt 10 = enable rising edge interrupt 11 = enable both falling or rising edge interrupt PortB.7 interrupt mode 00 = disable interrupt 01 = enable falling edge interrupt 10 = enable rising edge interrupt 11 = enable both falling or rising edge interrup t PortB.8 interrupt mode 00 = disable interrupt 01 = enable falling edge interrupt 10 = enable rising edge interrupt 11 = enable both falling or rising edge interrupt PortB.9 interrupt mode 00 = disable interrupt 01 = enable falling edge interrupt 10 = enable rising edge interrupt 11 = enable both falling or rising edge interrupt PortB.10 interrupt mode 00 = disable interrupt 01 = enable falling edge interrupt 10 = enable rising edge interrupt 11 = enable both falling or rising edge interrupt PortB.11 interrupt mode 00 = disable interrupt 01 = enable falling edge interrupt 10 = enable rising edge interrupt 11 = enable both falling or rising edge interrupt PortB.12 interrupt mode 00 = disable interrupt 01 = enable falling edge interrupt 10 = enable rising edge interrupt 11 = enable both falling or rising edge interrupt PortB.13 interrupt mode 00 = disable interrupt
5-4
PB2IM[1:0]
R/W
00
7-6
PB3IM[1:0]
R/W
00
9-8
PB4IM[1:0]
R/W
00
11-10
PB5IM[1:0]
R/W
00
13:12
PB6IM[1:0]
R/W
00
15-14
PB7IM[1:0]
R/W
00
17-16
PB8IM[1:0]
R/W
00
19-18
PB9IM[1:0]
R/W
00
21-20
PB10IM[1:0 ]
R/W
00
23:22
PB11IM[1:0 ]
R/W
00
25-24
PB12IM[1:0 ]
R/W
00
27-26
PB13IM[1:0 ]
R/W
00
CONFIDENTIAL
36
v1.0
RTL8181
01 = enable falling edge interrupt 10 = enable rising edge interrupt 11 = enable both falling or rising edge interrupt PB14IM[1:0 PortB.14 interrupt mode ] 00 = disable interrupt 01 = enable falling edge interrupt 10 = enable rising edge interrupt 11 = enable both falling or rising edge interrupt PB15IM[1:0 PortB.15 interrupt mode ] 00 = disable interrupt 01 = enable falling edge interrupt 10 = enable rising edge interrupt 11 = enable both falling or rising edge interrupt
29-28
R/W
00
31-30
R/W
00
Port B Interrupt Status Register (PBISR) Bit Bit Name Description 15-0 PBIP[15:0] Interrupt pending status. Self clear after read.
R/W R
InitVal 00
12. 802.11b WLAN Controller
RTL8181 integrates with a wireless LAN MAC and a direct sequence spread spectrum baseband processor, and is full compliance with IEEE 802.11 and IEEE 802.11b specifications. RTL8181 has on board A/D and D/A converters for analog I and Q inputs and outputs. Differential phase shift keying modulation schemes DBPSK and DQPSK, with data scrambling capability, are available along with complementary code keying to provide a variety of data rates. Both receive and transmit AGC functions obtain maximum performance in the analog portions of the transceiver. It also includes a built- in enhanced signal detector to alleviate severe multi-path effects. The target environment for 11Mbps is 125ns RMS delay spread. It also supports short preamble and antenna diversity. For security issues, RTL8181 has implemented a high performance internal WEP engine supporting up to 104-bits WEP. The WLAN controller is a DMA bus-master device, and uses descriptor-based buffer structure for packet transmission and reception. These features will definitely offload much CPU loading. RTL818 provides various interfaces for external RF module. Currently, it could interface with the RF modules as Intersil, RFMD and Philip. WLAN Controller register Set Virtual Address Size Name (byte)
0xBD40_0000 0xBD 40_0008 8 8 WLAN_ID WLAN_MAR
Description
ID Register : The ID register is only permitted to write by 4-byte access. Read access can be byte, word, or double word access. Multicast Register: The MAR register is only permitted to write by 4-bye access. Read access can be byte, word, or double word access. Timing Synchronization Function Timer Register Transmit Low Priority Descriptors Start Address (32-bit). (256-byte alignment) Transmit Normal Priority Descriptors Start Address (32-bit). (256-byte alignment) Transmit High Priority Descriptors Start Address (32-bit). (256-byte alignment) Basic Rate Set Register Basic Service Set ID Command Register Interrupt Mask Register Interrupt Status Register Transmit (Tx) Configuration Register Receive (Rx) Configuration Register Timer Interrupt Register. Once having written a nonzero value to
R/W
R/W R/W
0xBD40_0018 0xBD40_0020 0xBD40_0024 0xBD40_0028 0xBD40_002C 0xBD40_002E 0xBD40_0037 0xBD40_003C 0xBD40_003E 0xBD40_0040 0xBD40_0044 0xBD40_0048
8 4 4 4 4 6 1 2 2 4 4 4
WLAN_TSFTR WLAN_TLPDA WLAN_TNPDA WLAN_THPDA WLAN_BRSR WLAN_BSSID WLAN_CR WLAN_IMR WLAN_ISR WLAN_TCR WLAN_RCR WLAN_TINT
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
CONFIDENTIAL
37
v1.0
RTL8181
this register, the Timeout bit of WLAN_ISR register will be set whenever the least 32 bits of the WLAN_TSFTR reaches to this value. The Timeout bit will never be set as long as WLAN_TINT register is zero. Transmit Beacon Descriptor Start Address (32-bit) (256-byte alignment) Command Register Configuration Regist er 0 Configuration Register 2 Analog parameter Media Status Register Configuration Register 3 Configuration Register 4 TEST mode Register Security Configuration Register Beacon Interval Register Atim Window Register Beacon interrupt Interval Register Phy Delay Register PLCP header CRC16 error count Address register for Phy interface Write Data to Phy Read Data from Phy Phy Configuration Register WEP Default Key 0 Register WEP Default Key 1 Register WEP Default Key 2 Register WEP Default Key 3 Register Configuration Register 5 Transmit Priority Polling Register Contention Window Register Retry Count Register Receive Descriptor Start Address Register (32-bit) (256-byte alignment) Key Map MAC Address Key Map Key Value Key Map Config
0xBD40_004C 0xBD40_0050 0xBD40_0051 0xBD40_0053 0xBD40_0054 0xBD40_0058 0xBD40_0059 0xBD40_005A 0xBD40_005B 0xBD40_005F 0xBD40_0070 0xBD40_0072 0xBD40_0074 0xBD40_0078 0xBD40_007A 0xBD40_007C 0xBD40_007D 0xBD40_007E 0xBD40_0080 0xBD40_0090 0xBD40_00A0 0xBD40_00B0 0xBD40_00C0 0xBD40_00D8 0xBD40_00D9 0xBD40_00DC 0xBD40_00DE 0xBD40_00E4 0xBD40_0100 0xBD40_0106 0xBD40_0116
4 1 1 1 4 1 1 1 1 1 2 2 2 1 2 1 1 1 4 16 16 16 16 1 1 2 1 4 6 15 2
WLAN_TBDA WLAN_CR WLAN_CONFIG0 WLAN_CONFIG2 WLAN_ANAPARM WLAN_MSR WLAN_CONFIG3 WLAN_CONFIG4 WLAN_TESTR WLAN_SCR WLAN_BCNIT V WLAN_ATIMWND WLAN_BINTRITV WLAN_PHYDELAY WLAN_CRC 16ERR WLAN_PHYADDR WLAN_PHYDATAW WLAN_PHYDATAR WLAN_PHYCFG WLAN_DK0 WLAN_DK1 WLAN_DK2 WLAN_DK3 WLAN_ CONFIG5 WLAN_TPPOLL WLAN_ CWR WLAN_RETRYCTR WLAN_RDSAR WLAN_KMAR WLAN_KMKEY WLAN_KMC
R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R R/W R/W R/W R/W R/W R/W W R R R/W R/W R/W R/W
TSF timer register (WLAN_TSFTR) Bit Bit Name Description R/W 63-0 TSFT Timing Synchronization Function Timer: RTL8181 maintain a TSF timer with modules 2^64 R counting in increments of microseconds. The 8 octets are the timestamp field of beacon and probe response frame. Basic Rate Set Register (WLAN_BRSR) Bit Bit Name Description 15-9 Reserved 8 BPLCP 0:Long PLCP header for CTS/ACK packet. 1:Short PLCP header for CTS/ACK packet. 7-4 Reserved 3-0 MBR Maximum Basic Service Set Basic Rate. All control frames shall be transmitted at the rate that is less than or equal. bit0: 1M, bit1: 2M, bit2: 5.5M, bit3: 11M. Basic Service Set ID register (WLAN_BSSID) Bit Bit Name Description 47-0 BSSID Basic Service Set Identification: This register is written to by the driver after a NIC joins a network or creates an adhoc network.
R/W R/W
Command Register (WLAN_CR) This register is used for issuing commands to WLAN controller. These commands are issued by setting the corresponding bits for the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are provided here. 38
CONFIDENTIAL
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RTL8181
Bit 7:5 4 Bit Name RST Description Reserved Reset: Setting this bit to 1 forces the RTL8181 do the WLAN MAC reset. During reset reset state, it will disable the transmitter and receiver, and reinitializes the FIFOs. The values of WLAN_IDR and WLAN_MAR7 will have no changes. This bit is 1 during the reset operation, and is cleared to 0 when the reset operation is complete. Receiver Enable: When set to 1, and the receive state machine is idle, the receive machine becomes active. This bit will read back as 1 whenever the receive state machine is active. After initial power- up, software must insure that the receiver has completely reset before setting this bit. 1: Enable 0: Disable Transmitter Enable: When set to 1, and the transmit state machine is idle, the transmit state machine becomes active. This bit will read back as 1 whenever the transmit state machine is active. After initial power-up, software must insure that the transmitter has completely reset before setting this bit. 1: Enable 0: Disable Reserved R/W R/W
3
RE
R/W
2
TE
R/W
1-0
-
Interrupt Mask Register (WLAN_IMR) This register masks the interrupts that can be generated from the Interrupt Status Register. A hardware reset will clear all mask bits. Setting a mask bit allows the corresponding bit in the Interrupt Status Register to cause an interrupt. The Interrupt Status Register bits are always set to 1 if the condition is present, regardless of the state of the corresponding mask bit. Bit Bit Name Description R/W 15 TXFOVW Tx FIFO Overflow Interrupt: R/W 1: Enable 0: Disable 14 TimeOut Time Out Interrupt: R/W 1: Enable 0: Disable 13 BcnInt Beacon Time out Interrupt: R/W 1: Enable 0: Disable 12 ATIMInt ATIM Time Out Interrupt: R/W 1: Enable 0: Disable 11 TBDER Tx Beacon Descriptor Error Interrupt: R/W 1: Enable 0: Disable 10 TBDOK Tx Beacon Descriptor OK Interrupt: R/W 1: Enable 0: Disable 9 THPDER Tx High Priority Descriptor Error Interrupt: R/W 1: Enable 0: Disable 8 THPDOK Tx High Priority Descriptor OK Interrupt: R/W 1: Enable 0: Disable 7 TNPDER Tx Normal Priority Descriptor Error Interrupt: R/W 1: Enable 0: Disable 6 TNPDOK Tx Normal Priority Descriptor OK Interrupt: R/W 1: Enable 0: Disable 5 RXFOVW Rx FIFO Overflow Interrupt: R/W 1: Enable 0: Disable 4 RDU Rx Descriptor Unavailable Interrupt: R/W 39
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RTL8181
1: Enable 0: Disable Tx Low Priority Descrip tor Error Interrupt: 1: Enable 0: Disable Tx Low Priority Descriptor OK Interrupt: 1: Enable 0: Disable Rx Error Interrupt: 1: Enable 0: Disable Rx OK Interrupt: 1: Enable 0: Disable
3
TLPDER
R/W
2
TLPDOK
R/W
1
RER
R/W
0
ROK
R/W
Interrupt Status Register (WLAN_ISR) This register indicates the source of WLAN controller interrupt goes active. Enabling the corresponding bits in the Interrupt Mask Register (WLAN_IMR) allows bits in this register to produce an interrupt. When an interrupt is active, one of more bits in this register are set to a "1". The interrupt Status Register reflects all current pending interrupts, regardless of the state of the corresponding mask bit in the WLAN_IMR. Reading the WLAN_ISR clears all interrupts. Writing a 1 to any bit in this register will reset that bit. Bit Symbol Description R/W 15 TXFOVW Tx FIFO Overflow R/W 14 TimeOut Time Out: This bit is set to 1 when the least 32 bits of the TSFTR register reaches to the R/W value of the TimerInt register. 13 BcnInt Beacon Time Out Interrupt: When set, this bit indicates that the TBTT (Target Beacon R/W Transmission Time) has been reached after the value of the Beacon interrupt Interval register. 12 ATIMInt ATIM Time Out Interrupt: When set, this bit indicates that the ATIM window has been gone R/W after the value of the Beacon interrupt Interval register. 11 TBDER Transmit Beacon Priority Descriptor Error: Indicates that a packet of beacon priority descriptor R/W transmission was aborted due to an Rx beacon frame. 10 TBDOK Transmit Be acon Priority Descriptor OK: Indicates that a packet of beacon priority R/W descriptor exchange sequence has been successfully completed. 9 THPDER Transmit High Priority Descriptor Error: Indicates that a packet of high priority descriptor R/W transmission was aborted due to an SSRC (Station Short Retry Count) has reached SRL (Short Retry Limit), and an SLRC (Station Long Retry Count) has reached LRL (Long Retry Limit). 8 THPDOK Transmit High Priority Descriptor OK: Indicates that a packet of high priority descriptor R/W exchange sequence has been successfully completed. 7 TNPDER Transmit Normal Priority Descriptor Error: Indicates that a packet of normal priority R/W descriptor transmission was aborted due to an SSRC (Station Short Retry Count) has reached SRL (Short Retry Limit), and an SLRC (Station Long Retry Count) has reached LRL (Long Retry Limit). 6 TNPDOK Transmit Normal Priority Descriptor OK: Indicates that a packet of normal priority R/W descriptor exchange sequence has been successfully completed. 5 FOVW Rx FIFO Overflow: This bit set to 1 is caused by RDU, poor PCI performance, or R/W overloaded PCI traffic. 4 _RDU Rx Descriptor Unavailable: When set, this bit indicates that the Rx descriptor is currently R/W unavailable. 3 TLPDER Transmit Low Priority Descriptor Error: Indicates that a packet of low priority descriptor R/W transmission was aborted due to an SSRC (Station Short Retry Count) has reached SRL (Short Retry Limit), and an SLRC (Station Long Retry Count) has reached LRL (Long Retry Limit). 2 TLPDOK Transmit Low Priority Descriptor OK: Indicates that a packet of low priority descriptor R/W exchange sequence has been successfully completed. 1 RER Receive Error: Indicates that a packet has a CRC32 or ICV error. R/W 0 ROK Receive OK: In normal mode, indicates the successful completion of a packet reception. R/W
CONFIDENTIAL
40
v1.0
RTL8181
Transmit Configuration Register (WLAN_TCR) This register defines the Transmit Configuration for the WLAN controller. It controls such functions as loopback, heartbeat, auto transmit padding, programmable inter- frame gap, fill and drain thresholds, and maximum DMA burst size. Bit 31 30 Symbol CWMIN Description Contention Window minimum value: Set to 1 to indicate that Cwmin=8. Set to 0 to indicate that Cwmin=32. SEQGEN Sequence number generation switch. 0 - Enabled. Sequence number is generated by RTL8181. 1 - Disabled. Sequence number should be filled by software. Reserved SAT Set ACK Timeout: The EIFS, ACK and CTS timeouts are derived from the following equation: EIFS = 112/ACKrate + 252 1: ACKrate is dependent on the maximum of MBR (bits 1:0, BRSR) and Rx DATA/RTS rate. 0: ACKrate is fixed at 1Mbps. MXDMA2, 1, Max DMA Burst Size per Tx DMA Burst: This field sets the maximum size of trans mit 0 DMA data bursts according to the following table: 000: 16 bytes 001: 32 bytes 010: 64 bytes 011: 128 bytes 100: 256 bytes 101: 512 bytes 110: 1024 bytes 111: 2048 bytes DISCW Disable Contention Window Backoff: This bit indicates the existence of a backoff procedure during packet transmission. 1: No random backoff procedure 0: Uses IEEE 802.11 random backoff procedure ICV Append ICV: This bit indicates the existence of ICV appended at the end of an encipherment packet. 1: No ICV appended 0: ICV appended LBK1, LBK0 Loopback Test: There will be no packet on the TXI+/- and TXQ+/- lines under the Loopback test condition. The loopback function must be independent of the link state. 00: Normal operation 01: MAC Loopback 10: Baseband Loopback 11: Continue TX. CRC Append CRC32: This bit indicates the existence of a CRC32 appended at the end of a packet. 1: No CRC32 appended 0: A CRC32 is appended SRL RTS Retry Limit: Indicates the maximum retry times of RTS frame, data or management frame of length less than or equal to RTSThreshold. LRL Data Packet Retry Limit: Indicates the maximum retransmission times of Data or Management frame of length greater than RTSThreshold. R/W R/W
29-25 24
R/W
23-21
R/W
20
R/W
19
R/W
18-17
R/W
16
R/W
15-8 7-0
R/W R/W
Receive Configuration Register (WLAN_RCR) This register is used to set the receive configuration for the WLAN controller. Receive properties such as accepting error packets, runt packets, setting the receive drain threshold etc. are controlled here. Bit 31 30 Bit Name ONLYERLP KT ENCS2 Description R/W Early Receiving based on Packet Size: Early Receiving is only performed for packets with a R/W size greater than 1536 bytes. Enable Carrier Sense Detection Method 2 R/W
CONFIDENTIAL
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v1.0
RTL8181
29 28 27-24 23 Enable Carrier Sense Detection Method 1 Enable MAC Autoreset PHY Reserved Check BSSID, To DS, From DS Match Packet: When set to 1, the RTL8181 will check the Rx data type frame's BSSID, To DS and From DS fields, according to NETYPE (bits 3:2, MSR), to determine if it is set to Link ok at an Infrastructure or Adhoc network. APWRMGT Accept Power Management Packet: This bit will determine whether the RTL8181 will accept or reject packets with the power management bit set. 1: Accept 0: Reject ADD3 Accept Address 3 Match Packets: Set this bit to 1 to accept broadcast/multicast data type frames that Address 3 matching RTL8181's MAC address. This bit is valid only when NETYPE (bits 3:2, MSR) is set to Link ok in an Infrastructure network. AMF Accept Management Frame: This bit will determine whether the RTL8181 will accept or reject a management frame. 1: Accept 0: Reject ACF Accept Control Frame: This bit will determine whether the RTL8181 will accept or reject a control frame. 1: Accept 0: Reject ADF Accept Data Frame: This bit will determine whether the RTL8181 will accept or reject a data frame. 1: Accept 0: Reject Reserved RXFTH2, 1, Rx FIFO Threshold: This bit specifies the Rx FIFO Threshold level. When the number of 0 the received data bytes from a packet, which is being received into the Rx FIFO of the RTL8181, has reached to this level (or the FIFO has contained a complete packet), the receive PCI bus master function will begin to transfer the data from the FIFO to the ho st memory. This field sets the threshold level according to the following table: 000: Reserved 001: Reserved 010: 64 bytes 011: 128 bytes 100: 256 bytes 101: 512 bytes 110: 1024 bytes 111: No Rx threshold. The RTL8181 begins the transfer of data after havi ng received a whole packet into the FIFO. AICV Accept ICV Error Packet: This bit determines whether all packets with ICV error will be accepted or rejected. 1: Accept 0: Reject Reserved MXDMA2, 1, Max DMA Burst Size per Rx DMA Burst: This field sets the maximum size of the receive 0 DMA data bursts according to the following table: 000: 16 bytes 001: 32 bytes 010: 64 bytes 011: 128 bytes 100: 256 bytes 101: 512 bytes 110: 1024 bytes 111: Unlimited Reserved ACRC32 Accept CRC32 Error Packet: When set to 1, all packets with CRC32 error will be accepted. When set to 0, all packets with CRC32 error will be rejected. 1: Accept 42 ENCS1 ENMARP CBSSID R/W R/W R/W R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17-16 15-13
12
11 10-8
7-6 5
CONFIDENTIAL
v1.0
RTL8181
0: Reject Reserved Accept Broadcast Packets: This bit determines whether broadcast packets will be accepted or rejected. 1: Accept 0: Reject Accept Multicast Packets: This bit determines whether multicast packets will be accepted or rejected. 1: Accept 0: Reject Accept Physical Match Packets: This bit determines whether physical match packets will be accepted or rejected. 1: Accept 0: Reject Accept Destination Address Packets: This bit determines whether all packets with a destination address will be accepted or rejected. 1: Accept 0: Reject
4 3
AB
2
AM
1
APM
0
AAP
Command Register (WLAN_CR) This register is used for issuing commands to the WLAN controller. These commands are issued by setting the corresponding bits for the function. A warm software reset along with individual reset and enable/disable for transmitter and receiver are provided as well. Bit 7-6 Bit Name EEM Description These 2 bits select the operating mode. 00: Operating in network/host communication mode. 11: Before writing to the WLAN_CONFIG0, 1, 2, and 3 registers, the RTL8181 must be placed in this mode. This will prevent accidental change of the configurations of the WLAN controller. Reserved R/W R/W
5-0
-
Configuration Register 0 (WLAN_CONFIG0) Bit Bit Name Description 7-4 Reserved 3 Aux_Status Auxiliary Power Present Status: This bit indicates the existence of Aux. power. The value of this bit is fixed after each reset. 1: Aux. Power is present 0: Aux. Power is absent 2 Reserved 1-0 GL Geographic Location: These bits indicate the current operational region in which RTL8181 transmits and receives packets.. USA: 11, Europe: 10, Japan: 0 Configuration Register 2 (WLAN_CONFIG2) Bit Bit Name Description 7 LCK Locked Clocks: Set this bit to 1 to indicate that the transmit frequency and symbol clocks are derived from the same oscillator. 6 ANT Antenna Diversity: 1: Enable 0: Disable 5-4 Reserved 3 DPS Descriptor Polling State: Test mode.. 0: Normal working state. This is also the power-on default value. 1: Test Mode 2 PAPE_sign 1: RTL8181 will advance PAPE_time to enable the PAPE pin when Tx data 0: RTL8181 will delay PAPE_time to enable the PAPE pin when Tx data 1-0 PAPE_time These two bits indicate that the RTL8181 has enabled the PAPE pin in s.
R/W R/W
R/W
R/W R/W R/W
R/W R/W R/W
CONFIDENTIAL
43
v1.0
RTL8181
Media Status Register (WLAN_MSR) This register allows configuration of device and PHY options, and provides PHY status information. Bit 7-4 3-2 1-0 Bit Name NETTYPE Description Reserved Network Type and Link Status: The values of these bits are written by the driver. 10: Infrastructure client, 01: Ad hoc, 11: Access Point, 00: No link Reserved R/W R/W -
Configuration Register 3 (WLAN_CONFIG3) Bit Bit Name Description 7 Reserved 6 PARM_En Parameter Write Enable: Setting this bit to 1 and the WLAN_CR register EEM1=EEM0=1 enables the WLAN_ANAPARM register to be written via software. 4-1 -Reserved 0 FBtBEn Fast Back to Back Enable: 1: Enable 0: Disable Configuration Register 4 (WLAN_CONFIG4) Bit Bit Name Description 7 VCOPDN VCO Power Down: 1: VCO Power Down mode. Setting this bit will enable VCOPDN pin and turn off the external RF front end power (includ ing VCO) and most of the internal power of the RTL8181. 0: Normal working state. This is the power-on default value. 6 PWROFF Power Off: 1: Power Off mode. Turn off the external RF front end power (excluding VCO) and most of the internal power of the RTL818 1. 0: Normal working state. This is the power-on default value. 5 PWRMGT Power Management: 1: Power Management mode. Set Tx packet's power management bit to 1 include control type frame. 0: Normal working state. This is the power-on default value. 4-2 Reserved 1-0 RFTYPE Radio Front End Programming Method: The combination of these two bits indicate what kind of the RF module is being used with the RTL8181. 11: Philips, 10: RFMD, 01: Intersil
R/W R/W
R/W
R/W R/W
R/W
R/W
R/W
Security Configuration Register (WLAN_SCR) Bit Bit Name Description 7-6 Reserved 5-4 KM Key Mode: The combination of these two bits indicate what kind of security scheme is being used. 01: WEP40, 01: WEP104 3-2 Reserved 1 TXSECON TX Security ON: Set this bit to 1 to turn on the option security scheme of the Tx path. This bit is written by software and is invalid when WEP40 (bit 7, WLAN_CONFIG0), and WEP104 (bit 6, WLAN_CONFIG0) are set to 0. 0 RXSECON RX Security ON: Set this bit to 1 to turn on the option security scheme of the Rx path. This bit is written by software and is invalid when WEP40 (bit 7, WLAN_CONFIG0), and WEP104 (bit 6, WLAN_CONFIG0) are set to 0.
R/W R/W
R/W
R/W
CONFIDENTIAL
44
v1.0
RTL8181
Beacon Interval Register (WLAN_BCNITV) Bit Bit Name Description R/W 15-10 Reserved 9-0 BcnItv Beacon Interval: The Beacon Interval represents the number of time units (1 TU = R/W 1024s) between target beacon transmission times (TBTTs). This register is written by the driver after starting a BSS/IBSS or joining IBSS network. ATIM Window Register (WLAN_ATIMWND) Bit Bit Name Description 15-10 -Reserved 9-0 AtimWnd This r egister indicates the ATIM Window length in TU. It is written by the driver after the NIC joins or creates an adhoc network.
R/W R/W
Beacon Interrupt Interval Register (WLAN_BINTRITV) Bit Bit Name Description R/W 15-10 Reserved 9-0 BintrItv This timer register will generate BcnInt (bit 13, ISR) at a setting time interval before TBTT to R/W prompt the host to prepare the beacon. The units of this register is microseconds. It is written by the driver after the NIC joins a network or creates an adhoc network. Atim Interrupt Interval Register (WLAN_ATIMTRITV) Bit Bit Name Description R/W 15-10 Reserved 9-0 AtimtrItv This timer register will generate ATIMInt (bit 12, ISR) at a setting time interval before the R/W end of the ATIM window in an adhoc network. The units of this register is microseconds. It is written by the driver after the NIC joins a network or creates an adhoc network. Phy Delay Register (WLAN_PHYDELAY) Bit Bit Name Description R/W 7-3 Reserved 2-0 PhyDelay Physical Layer Delay Time: These three bits represent the delay time in s between the MAC R/W and RF front end when Tx data. Default Key 0 Register (WLAN_DK0) Bit Bit Name Description R/W 127-104 Reserved 103-0 DK0 Default Key 0: These 104 bits (bits 103:0) indicate the default 104-bit WEP key, which the R/W ID is 0 when KM (bits 5:4, SCR) is set to WEP104, the 24 most significant bits (bits 127:103) will be reserved. The 40 least significant bits (bits 39:0) indicate the default 40-bit WEP key, which the ID is 0 when KM is set to WEP40, and the 64 most significant bits (bits 103:40) will be reserved. This register is only permitted to read/write by 4-byte access. Default Key 1 Register (WLAN_DK1) Bit Bit Name Description R/W 127-104 Reserved 103-0 DK1 Default Key 1: These 104 bits (bits 103:0) indicate the default 104-bit WEP key, which the R/W ID is 1 when KM (bits 5:4, SCR) is set to WEP104, the 24 most significant bits (bits 127:103) will be reserved. The 40 least significant bits (bits 39:0) indicate the default 40-bit WEP key, which the ID is 1 when KM is set to WEP40, and the 64 most significant bits (bits 103:40) will be reserved. This register is only permitted to read/write by 4-byte access. Default Key 2 Register (WLAN_DK2) Bit Bit Name Description 127:104 Reserved 103:0 DK2 Default Key 2: These 104 bits (bits 103:0) indicate the default 104-bit WEP key, which the
R/W R/W
CONFIDENTIAL
45
v1.0
RTL8181
ID is 2 when KM (bits 5:4, SCR) is set to WEP104, the 24 most significant bits (bits 127:103) will be reserved. The 40 least significant bits (bits 39:0) indicate the default 40-bit WEP key, which the ID is 2 when KM is set to WEP40, and the 64 most significant bits (bits 103:40) will be reserved. This register is only permitted to read/write by 4-byte access. Default Key 3 Register (WLAN_DK3) Bit Bit Name Description R/W 127-104 Reserved 103-0 DK3 Default Key 3: These 104 bits (bits 103:0) indicate the default 104-bit WEP key, which the ID R/W is 3 when KM (bits 5:4, SCR) is set to WEP104, the 24 most significant bits (bits 127:103) will be reserved. The 40 least significant bits (bits 39:0) indicate the default 40-bit WEP key, which the ID is 3 when KM is set to WEP40, and the 64 most significant bits (bits 103:40) will be reserved. This register is only permitted to read/write by 4-byte access. Configuration Register 5 (WLAN_CONFIG5) This register, unlike other Configuration registers, is not protected by the Command register. Therefore, there is no need to enable the Config register write prior to writing to Config5. Bit Bit Name Description R/W 7 TX_FIFO_OK Built in Self Test for TX FIFO: R 1: OK 0: Fail 6 RX_FIFO_OK Built in Self Test for RX FIFO: R 1: OK 0: Fail 5 CALON Calibration ON. R/W 1: Activate the calibration cycle, and hold AGCRESET pin to high 0: Put AGCRESET pin to ground 4-0 Reserved Transmit Priority Polling Register (WLAN_TPPOLL) Bit Bit Name Description 7 BQ Beacon Queue Polling: The RTL8181 will clear this bit automatically after a beacon packet has been transmitted or received. Writing to this bit has no effect. 6 HPQ High Priority Queue Polling: Write a 1 to this bit by software to notify the RTL8181 that there is a high priority packet(s) waiting to be transmitted. The RTL8181 will clear this bit automatically after all high priority packets have been transmitted. Writing a 0 to this bit has no effect. 5 NPQ Normal Priority Queue Polling: DPS (bit3, Config 2) set to 0: The RTL8181 will clear this bit automatically after all normal priority packets have been transmitted or received. Writing to this bit has no effect. DPS (bit3, Config 2) set to 1: Write a 1 to this bit by software to notify the RTL8181 that there is a normal priority packet(s) waiting to be transmitted. The RTL8181 will clear this bit automatically after all normal priority packets have been transmitted. Writing a 0 to this bit has no effect. 4 LPQ Low Priority Queue Polling: Write a 1 to this bit by software to notify the RTL8181 that there is a low priority packet(s) waiting to be transmitted. The RTL8181 will clear this bit automatically after all low priority packets have been transmitted. Writing a 0 to this bit has no effect.
R/W W
W
W
W
CONFIDENTIAL
46
v1.0
RTL8181
3 2 1 SBQ SHPQ SNPQ Stop Beacon Queue: Write a 1 to this bit by software to notify the RTL8181 to stop the DMA mechanism of the Beacon Queue. This bit is invalid when DPS (bit3, Config 2) is set to 1. Stop High Priority Queue: Write a 1 to this bit by software to notify the RTL8181 to stop the DMA mechanism of the High Priority Queue. Stop Normal Priority Queue: Write a 1 to this bit by software to notify the RTL8181 to stop the DMA mechanism of the Normal Priority Queue. This bit is invalid when DPS (bit3, Config 2) is set to 1. Stop Low Priority Queue: Write a 1 to this bit by software to notify the RTL8181 to stop the DMA mechanism of the Low Priority Queue. W W W
0
SLPQ
W
Contention Window Register (WLAN_CWR) Bit Bit Name Description 15-10 Reserved 9-0 CW Contention Window: This register indicates the number of contention windows before transmitting a packet. Retry Count Register (WLAN_RETRYCTR) Bit Bit Name Description 7-0 RetryCT Retry Count: This register indicates the number of retry counts when a packet transmit is completed. Receive Descriptor Start Address Register (WLAN_RDSAR) Bit Bit Name Description 31-0 RDSA Receive Descriptor Start Address: This is a 32-bit address.
R/W R
R/W R
R/W R/W
WEP Key mapping
The WEP key table will contain 64 entries that include the key to be used to encrypt the transmit packets and decrypted the received frame. Each entry contains the MAC address, associated key value, key type (may be 40bits or 104 bits) and a key- valid flag. To set/get an entry to/from the table, you can't access the table memory directly. Instead, the access should go through registers because the key table is embedded in ASIC. When reading/writing the entry, you have to specify which table entry you are going to access by an index value defined in register KeyMapIdx. For example, if you wants to update a table entry, you need set MAC address in keyMapAddr, set key value in KeyMapKey, specify key type (40bits or 104bits) in KeyMapType , set table index in keyMapIdx, assert the valid flag in KeyMapValid, and write `1' in KeyMapOp as ' write' operation. After all these values are set, you have to set `1' in register KeyMapPoll bit to tell WLAN controller to process the request. Then, you may wait the WLAN controller to accomplish the operation by polling KeyMapPoll bit until it is cleared. There is no default value for these registers in initialization. Therefore, you have to reset the KeyMapValid flag for those entries you did not used. Key Map MAC Address (WLAN_KMAR) Bit Bit Name Description 47-0 KeyMapAddr MAC address Key Map Key Value (WLAN_KMKEY) Bit Bit Name Description 127-0 KeyMapKey WEP key value Key Map Config (WLAN_KMC) Bit Bit Name Description 15-10 KeyMapIdx Key map index, specify which table entry to read or write. 9-8 KeyMapType Key value type. 0 - 40bits, 1-104bits, 2-3 reserved. 7 KeyMapValid Valid flag. If this bit is `1', it indicates the table entry, indexed by KeyMapIdx, is valid. Bit
R/W R/W
R/W R/W
R/W R/W R/W R/W
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`0' implies the entry is invalid. Operation for writing or reading key value. Value `1' indicates to set key value, `0' means to R/W get key value. R/W KeyMapPoll Polling bit of read/write key. 1. Set `1' to make RTL8181 begin to read/write the value of key table, which entry index is specified in KeyMapIdx. 2. RTL8181 will clear the bit atomically after the operation is completed. 3. Writing `0' to this bit has no effect. Reserved KeyMapOp
6 5
4-0
Packet Buffering RTL8181 WLAN controller incorporates two independent FIFOs for transferring data to/from the system interface and from/to the network. The FIFOs, providing temporary storage of data freeing the host system from the real- time demands of the network. The way in which the FIFOs are emptied and filled is controlled by the FIFO threshold values in the Receive Configuration registers. These values determine how full or empty the FIFOs must be before the device requests the bus. Once RTL8181 requests the bus, it will attempt to empty or fill the FIFOs as allowed by the respective MXDMA settings in the Transmit Configuration and Receive Configuration registers. Transmit Buffer Manager The buffer management scheme used on the WLAN controller allows quick, simple and efficient use of the frame buffer memory. The buffer management scheme uses separate buffers and descriptors for packet information. This allows effective transfers of data to the transmit buffer manager by simply transferring the descriptor information to the transmit queue. The Tx Buffer Manager DMAs packet data from system memory and places it in the 4KB transmit FIFO, and pulls data from the FIFO to send to the Tx MAC. Multiple packets may be present in the FIFO, allowing packets to be transmitted with short interframe space. Additionally, once RTL8181 requests the bus, it will attempt to fill the FIFO as allowed by the MXDMA setting. The Tx Buffer Manager process also supports priority queuing of transmit packets. It handles this by drawing from two separate descriptor lists to fill the internal FIFO. If packets are available in the high priority queues, they will be loaded into the FIFO before those of low priority. Receive Buffer Manager The Rx Buffer Manager uses the same buffer management scheme as used for transmits. The Rx Buffer Manager retrieves packet data from the Rx MAC and places it in the 2KB receive data FIFO, and pulls data from the FIFO for DMA to system memory. The receive FIFO is controlled by the FIFO threshold value in RXFTH. This value determines the number of long words written into the FIFO from the MAC unit before a DMA req uest for system memory occurs. Once the RTL8181 gets the bus, it will continue to transfer the long words from the FIFO until the data in the FIFO is less than one long word, or has reached the end of the packet, or the max DMA burst size is reached, as se t in MXDMA.
13. Package Information
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RTL8181 Package outline for 208 LQFP(28*28*1.4mm)
Note:
Symbol A A1 A2 b c D E e HD HE L L1 y ? Dimension in Min Typ 0.136 0.144 0.004 0.010 0.119 0.128 0.004 0.008 0.002 0.006 1.093 1.102 1.093 1.102 0.012 0.020 1.169 1.205 1.169 1.205 0.010 0.020 0.041 0.051 0 inch Max 0.152 0.036 0.136 0.012 0.010 1.112 1.112 0.031 1.240 1.240 0.030 0.061 0.004 12 Dimension in mm Min Typ Max 3.45 3.65 3.85 0.10 0.25 0.91 3.02 3.24 3.46 0.10 0.20 0.30 0.04 0.15 0.26 27.75 28.00 28.25 27.75 28.00 28.25 0.30 0.50 0.80 29.70 30.60 31.50 29.70 30.60 31.50 0.25 0.50 0.75 1.05 1.30 1.55 0.10 0 12 1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion. 3.Controlling dimension: Millimeter 4.General appearance spec. should be based on final visual inspection spec. TITLE : 208L QFP ( 28x28 mm**2 ) FOOTPRINT 2.6mm PACKAGE OUTLINE DRAWING LEADFRAME MATERIAL: APPROVE DOC. NO. 530-ASS-P004 VERSION 1 PAGE 22 OF 22 CHECK DWG NO. Q208 - 1 DATE APR. 11.1997 REALTEK SEMI-CONDUCTOR CO., LTD
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RTL8181 Package outline for TFBGA 292 BALL(17*17 mm)
Symbol A A1 A2
Dimension in Min Nom ----0.25 0.30 0.84 0.89
mm Dimension in Max Min Nom 1.30 ----0.35 0.010 0.012 0.94 0.033 0.035 0.665 0.665 ------0.014
inch Max 0.051 0.014 0.037
1. CONTROLLING DIMENSION : MILLIMETER 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. 4. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 5. REFERENCE DOCUMENT : JEDEC MO-205. 6. THE PATTERN OF PIN 1 FIDUCIAL IS FOR REFERENCE ONLY.
c 0.32 0.36 0.40 D 16.90 17.00 17.10 E 16.90 17.00 17.10 D1 --15.20 --E1 --15.20 --e --0.80 --b 0.35 0.40 0.45 aaa 0.10 bbb 0.10 ccc 0.12 ddd 0.15 eee 0.08 MD/ME 20/20
0. 013 0.014 0.016
0.669 0.673 0.669 0.673 0.598 --0.598 --0.031 --0.016 0.018 0.004 0.004 0.005 0.006 0.003 20/20
TITLE : 292LD TFBGA ( 17x17mm) PACKAGE OUTLINE SUBSTRATE MATERIAL: BT RESIN APPR. ENG. QM. CHK. DWG. REALTEK SEMI-CONDUCTOR CO., LTD
DWG NO.. Rev NO PRODUCT CODE DATE. SHT No.
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